Purchase VG36256801A, In-stock VG36256801A From SeekIC.
Part Number: VG36256801A
Description: The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank,8,388,60...
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VG36256801A
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DataSheet
General Description
VG36256801A General Description
The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank,8,388,608 - word x 8 - bit x 4 - bank, or 4,194,304 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
VG36256801A Maximum Ratings
| Parameter | Symbol | Value | Unit |
| Voltage on any pin relative to Vss |
VIN,VOUT | -0.5 to + 4.6 | V |
| Supply voltage relative to Vss | VDD,VDDQ | -0.5 to + 4.6 | V |
| Short circuit output current | IOUT | 50 | mA |
| Power dissipation | PD | 1.0 | W |
| Operating temperature | TOPT | 0 to + 70 | · |
| Storage temperature | TSTG | -55 to + 125 | · |
VG36256801A Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A13 & A14 (Bank select)
• Each Banks can operate simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM, LDQM, UDQM
• 8,192 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A13 & A14 (Bank select)
• Each Banks can operate simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM, LDQM, UDQM
• 8,192 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
VG36256801A Connection Diagram
VG36256801A
PDF/DataSheet Download
- Datasheet: VG36256801A
- File Size: 967536 KB
- Manufacturer: VML [Vanguard International Semiconductor]
- Click here to Download
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