VM007

The VM007 has the following features including Complete cryptographic processing system on a single chip;Supports clock frequencies to 30MHz;Capable of encrypting/decrypting 192 Mbits per second using Electronic Codebook (ECB) or Cipher Block Chaining (CBC);Class 3 ESD protection (above 4000V);Pending validation by National Institute of Standards and Technology (NIST);Internal RISC sequencer with on-chip RAM and ROM program memory;Advanced security features;Automatic built-in self-test after reset;84-lead ceramic or plastic leaded chip carrier (LDCCC, PLCC) packages;1.0-micron two layer metal CMOS technology; ensuring highly reliable operation.

The VM007 Data Encryption Processor is a programmable integrated circuit that provides a complete cryptographic system on a single chip. h contains a hardware implementation of the Data Encryption Standard (DES), a RISC-based sequencer, data storage registers, and ROM-based microprogram. It is designed to provide very high data and key processing rates,flexible I/O interfacing, and advanced security features.The VM007 is manufactured using VLSI's 1.0-micron CMOS technology and is available in an 84-lead ceramic or plastic leaded chip carrier. All inputs and outputs are TTL compatible.In the read mode, the circuit operates as a low-noise differential amplifier. The write current source is fumed off and the write data flip-flop is set. The selected head provides a differential input. The RDX and RDY pins provide differential emitter follower outputs which are in phase with the X and Y inputs.Write current is deactivated for both the read and the idle mode so that external gating is not required.

The VM007 is a complete cryptographic processing system on a single chip.The device is designed to achieve high data through-put while providing advanced security features and superior reliability. In addition, the chip offers an optional programming interface to give the user flexibility to process complex cryptographic functions. These features make the VM007 uniquely able to solve demanding applications in high performance computing systems.Once the IRQ pin becomes inactive, the interrupt routine will terminate immediately, and the RISC will branch to the initial address stored in the Control Register. h is not necessary to reload the CR before the interrupt routine terminates.