VM6400

The VM6400 has the following features including Analog Portion of High-Performance Sampled-Amplitude Digital ReadlWrite Channel;Operation from 16 to 64 Mbitslsec;Compatible with 213 (1,7) RLL Code;Supports Zoned-Density Recording;Digitally Controlled VGA and VFO;Programmable Active Filter with Variable Cutoff and Boost;Four Gated Servo Peak Detectors;6-Bit 96 MSamples/sec Flash ADC;Write Precompensation;Extensive Power Management Techniques;Operation from Single +5 V Supply;Supports Monolithic, Composite, Thin-Film, MIG and MR Heads;Available in a 64-lead POFP;Fabricated Using VTC's Advanced PolarM05 Process;Can Be Used with any Compatible Digital Part;Only Five External Components Needed for Operation.

The VM6400 is the analog half of a digital readlwrite channel chip set for hard disk drive applications. The VM6400's designed to interface to the Cirrus Logic CL-SH4400, but can be used with any compatibly designed digital chip. The chip provides for a high degree of user programmability allowing the customization of the chip to suit any channel specific application.The VM6400 is fabricated in VTC's PolarMOS process which offers high-performance bipolar and MOS devices for precision analog circuitry, and low-power CMOS technology for digital control functions. The VM6400 is available in a 64-pin Plastic Quad Flatpack. An analog automatic gain control (AGC) servo loop allows for the processing of servo burst information using the VGA and active filter, along with an envelope detector, charge pump, and off-chip capacitor. Peak detectors, driven by a full-wave rectifier (FWR), provide analog voltages representing the magnitudes of the A, B, C, and D servo signals relative to an on-chip generated voltage reference, SVREF. A set of four digital inputs, SC(3:0), which are strobed into the chip with REFCLK,control the sampling of the servo data.

The ENA pin of VM6400 provides for a Sleep mode, or an optional Nap mode, so that the chip can be put into a low power mode, as well as a Reset mode so that the chip can be reinitialized. A number of control register bits can disable the various blocks of the chip both independently and as a function of mode. The read gate and write gate pins, RGN and WGN, control the mode of the chip (Read, Write, or Idle). The serial enable pin (SERENA), along with the serial clock (SERCLK) and serial data pin (SERDAT), controls the loading and readback of the control register via the serial interface. Due to pin limitations,SERCLK and SERDAT are multiplexed with ENDATO and EN-DAT1 respectively.