VP520S

Lower Power, pin compatible replacement for VP520
Converts CCIR601 luminance and chrominance to CIF or QCIF resolution, and vice versa, using a 27MHz system clock.
Luminance and chrominance channels have their own sets of horizontal and vertical filters with on chip line stores
Each filter set may be configured to either decimate or interpolate.
NTSC line insertion or removal mode
Produces / expects CIF/QCIF data in macroblock format.
120 Pin QFP Package

The VP520S is designed to convert 16 bit multiplexed luminance and chrominance data between CCIR601 and CIF/ QCIF resolutions. Vertical and horizontal FIR filters are provided, with the vertical filters supported by on chip line stores. The coefficients used by the filters are user definable, and are down loaded from an independent host data bus. An internal address generator supports an external DRAM frame store, and also provides line to macroblock conversion.

When producing CIF or QCIF video the horizontal filters precede the vertical filters, and are provided with between 8 and 16 taps. The VP520S vertical filters are provided with four CIF line delays which allow a 5 tap filter to be implemented. When producing QCIF the available RAM is used to provide six line delays, which thus allows 7 tap filters to be used.

When the VP520S device is producing CCIR601 video, the incoming data must be in macroblock format, and the vertical filters precede the horizontal filters The inputs are firstly written to a external CIF sized frame store, and are read out in line format. The VP520S will support two complete frame stores, and allows the CIF/QCIF data to be read out twice in order to produce two interlaced fields of video.

The VP520S supports the conversion between CIF/QCIF and NTSC video. An extra line is produced for every five lines
when producing CIF data, and one line in six is removed when producing NTSC video. Poly phase filters are used to provide the correct decimation and interpolation ratios.