Virtex-II 1.5V

Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the evice. These are stress atings only, and functional operation of the device at these or any other conditions beyond those listed nder Operating Conditions s not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect  evice reliability.
2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx ebsite.
3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification hat would imply that the evice is not PCI compliant.

The Virtex-II family includes platform FPGAs developed for igh performance from low-density to high-density designs hat are based on IP cores and customized modules. The Virtex-II family delivers complete solutions for telecommunication, ireless, networking, video, and DSP applications, including CI, LVDS, and DDR interfaces.

The leading-edge 0.15 m/0.12 m CMOS 8-layer metal rocess and the Virtex-II architecture are optimized for high peed with low power consumption. Combining a wide variety f flexible features and a large range of densities up to  million system gates, the Virtex-II family enhances programmable ogic design capabilities and is a powerful alternative o mask-programmed gates arrays. As shown in able 1, the QPro Virtex-II family comprises three members, anging from 1M to 6M system gates.

wire-bond interconnects, flip-chip interconnect of Virtex-II is used in ome of the CGA offerings. The use of flip-chip interconnect ffers more I/Os than is possible in wire-bond versions of he similar packages. Flip-chip construction of Virtex-II offers the combination f high pin count with high thermal capacity.

Table 2 shows the maximum number of user I/Os available. he Virtex-II device/package combination table (Table 5 on age 5) details the maximum number of I/Os for each evice and package using wire-bond or flip-chip technology.