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W3EG6433S-BD4

Features: ·DDR200, DDR266 and DDR333 ·Double-data-rate architecture ·Bi-directional data strobes (DQS) ·Differential clock inputs (CK & CK#) ·Programmable Read Latency 2,2.5 (clock) ·Programmable Burst Length (2,4,8) ·Programmable Burst type (sequential & interleave) ·Edge aligned data out...

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SeekIC No. : 004544704 Detail

W3EG6433S-BD4: Features: ·DDR200, DDR266 and DDR333 ·Double-data-rate architecture ·Bi-directional data strobes (DQS) ·Differential clock inputs (CK & CK#) ·Programmable Read Latency 2,2.5 (clock) ·Programmabl...

W3EG6433S-BD4 Data Sheet

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Part Number:
W3EG6433S-BD4
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·DDR200, DDR266 and DDR333
·Double-data-rate architecture
·Bi-directional data strobes (DQS)
·Differential clock inputs (CK & CK#)
·Programmable Read Latency 2,2.5 (clock)
·Programmable Burst Length (2,4,8) 
·Programmable Burst type (sequential & interleave)
·Edge aligned data output, center aligned data input
·Auto and self refresh
·Serial presence detect
·Power supply: 2.5V ± 0.20
·JEDEC standard 200 pin SO-DIMM package
    Package height options:
    AD4:  35.5mm (1.38")
    BD4:  31.75mm (1.25")


Specifications

Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN , V OUT
-0.5 to 3.6
V
Voltage on V CC
supply relative to VSS
VCC , VCCQ
-1.0 to 3.6
V
Storage Temperature
TSTG
-55 to +150
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA

Note:
 Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
 Functional operation should be restricted to recommended operating condition.
 Exposure to higher than recommended voltage for extended periods of time could 
 affect device reliability.


Description

The W3EG6433S-BD4 is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The W3EG6433S-BD4 consists of eight 32Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on oth edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high formance  applications.




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