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W3EG6462S-D3

Features: Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi edBi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & in...

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SeekIC No. : 004544707 Detail

W3EG6462S-D3: Features: Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi edBi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read ...

W3EG6462S-D3 Data Sheet

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Part Number:
W3EG6462S-D3
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/18

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Product Details

Description



Features:

Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifi ed
 Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166 MHz)
• VCC = VCCQ = +2.6V ±0.1V (200 MHz)
Standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") MAX


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V
Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 A
Storage Temperature TSTG 250
Power Dissipation PD 30
Short Circuit Current IOS - 65 to 175


Note:
Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability




Description

The W3EG6462S is a 2x32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of sixteen 32Mx8 DDR  SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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