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W3EG72125S-D3

Features: * Double-data-rate architecture* Clock Speeds of 100MHz, 133MHz and 166MHz* Bi-directional data strobes (DQS)* Differential clock inputs (CK & CK#)* Programmable Read Latency 2,2.5 (clock)* Programmable Burst Length (2,4,8)* Programmable Burst type (sequential & interleave)* Edge...

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SeekIC No. : 004544714 Detail

W3EG72125S-D3: Features: * Double-data-rate architecture* Clock Speeds of 100MHz, 133MHz and 166MHz* Bi-directional data strobes (DQS)* Differential clock inputs (CK & CK#)* Programmable Read Latency 2,2.5 (cl...

W3EG72125S-D3 Data Sheet

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Part Number:
W3EG72125S-D3
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

* Double-data-rate architecture
* Clock Speeds of 100MHz, 133MHz and 166MHz
* Bi-directional data strobes (DQS)
* Differential clock inputs (CK & CK#)
* Programmable Read Latency 2,2.5 (clock)
* Programmable Burst Length (2,4,8)
* Programmable Burst type (sequential & interleave)
* Edge aligned data output, center aligned data input
* Auto and self refresh
* Serial presence detect
* Dual Rank
* Power supply: VCC = 2.5V ± 0.2V
* JEDEC standard 184 pin DIMM package
• Package height options:JD3: 30.48mm (1.20") and AJD3: 28.70mm (1.13")


Specifications

Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 to 3.6
V
Storage Temperature
TSTG
-55 to +150
Power Dissipation
PD
9
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The W3EG72125S-D3 is a 2x64Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The W3EG72125S-D3 consists of eighteen 2x64Mx4 stacked (36 components), in 66 pin TSOP package mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.




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