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W3EG72126S-D3

Features: •Double-data-rate architecture•DDR200, DDR266 and DDR333:• JEDEC design specifi cations•Bi-directional data strobes (DQS)•Differential clock inputs (CK & CK#)•Programmable Read Latency 2,2.5 (clock)•Programmable Burst Length (2,4,8)R...

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SeekIC No. : 004544716 Detail

W3EG72126S-D3: Features: •Double-data-rate architecture•DDR200, DDR266 and DDR333:• JEDEC design specifi cations•Bi-directional data strobes (DQS)•Differential clock inputs (CK ...

W3EG72126S-D3 Data Sheet

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Part Number:
W3EG72126S-D3
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•Double-data-rate architecture
•DDR200, DDR266 and DDR333:
• JEDEC design specifi cations
•Bi-directional data strobes (DQS)
•Differential clock inputs (CK & CK#)
•Programmable Read Latency 2,2.5 (clock)
•Programmable Burst Length (2,4,8)
•Programmable Burst type (sequential & interleave)
•Edge aligned data output, center aligned data input.
•Auto and self refresh
•Serial presence detect
•Power supply: VCC = 2.5V ± 0.20V
•JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
• Consult factory for availability of lead-free products.


Specifications

Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
VIN, VOUT
VCC, VCCQ
-0.5 to 3.6
-1.0 to 3.6
V
V
Storage Temperature
Power Dissipation
Short Circuit Current
TSTG
PD
IOS
-55 to +150
27
50

W
mA
Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The W3EG72126S-D3 is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The W3EG72126S-D3 consists of eighteen 128Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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