W65C51S

• Low power CMOS N-well silicon gate technology
• Replacement for CMD / GTE Harris / MOS Technology / GE/RCA / Synertek / Motorola / Rockwell R6551, 65SC51, 65C51, 6551, CPD65C51, 6551, 6850
• Full duplex operation with buffered receiver and transmitter
• Data set/modem control functions
• Internal baud rate generator with 15 programmable baud rates (50 to 19,200)
• Program-selectable internally or externally controlled receiver rate
• Programmable word lengths, number of stop bits and parity bit generation and detection
• Programmable interrupt control
• Program reset
• Program-selectable serial echo mode
• Two chip selects
• 2 or 4 MHz operation
• 5.0 VDC ± 5% supply requirements
• 28 pin plastic DIP package
• 28 pin PLCC package
• Full TTL compatibility
• Compatible with 65xx and 68xx microprocessors

The WDC CMOS W65C51S Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor based systems and serial communication data sets and modems.

The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at 1/16 times an external clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity; 1, 1½ or 2 bit stops.

The ACIA is designed for maximum-programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit the MPU to easily select the W65C51S operating modes and data checking parameters and determine operational status.

The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTSB line, receiver interrupt control and the state of the DTRB line.

The Control Register controls the number of stop bits, word length, receiver clock source and baud rate.

The Status Register indicates the states of the IRQB, DSRB, and DCDB lines, Transmitter and Receiver Data Registers and Overrun, Framing and Parity Error conditions.

The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.