W83C554F

The W83C554F Enhanced System I/O (SIO) Controller with PCI Arbiter is a highly integrated device intended for use in any Peripheral Component Interconnect (PCI) system, supporting x86 or PowerPC (non-x86) type microprocessors. It supports all PCI 2.1 compliant CPU bridge implementations and directly interfaces with PCI and ISA industry standard buses, including two direct drive IDE channels supporting up to four peripherals.

The W83C554F is a universal PCI device which can be used with many CPU-to-PCI bridge solution. The W83C554F includes 32-bit ISA DMA addressing (rather than 24-bit) to simplify its use in systems using re-compiled versions of 32-bit operating systems (such as Windows NT running on PowerPC, Alpha, or other RISC CPU).

The peripheral controller integrated into the W83C554F includes two enhanced seven channel 82C37A 32-bit DMA controllers that support fast DMA transfers with a four byte line buffer to isolate the PCI bus from the ISA bus, enhancing performance. Both DMA controllers support scatter/gather data transfer capability.

The W83C554F Enhanced SIO controller provides the bridge between the PCI bus and the ISA expansion bus. It also
integrates a PCI bus master IDE controller, an eight master PCI arbiter (which may be disabled if desired) and many of the common I/O functions found in today's ISA based PC systems. The W83C554F incorporates the logic for a complete PCI interface (master and slave) and ISA interface (master and slave). Also included is PCI and ISA arbitration, 14 level interrupt controller, a 16-bit BIOS timer, three programmable counter/timers, non-maskable-interrupt (NMI) control logic and register support for power management break events.

The built-in Enhanced PCI IDE Controller is a highly integrated dual port controller, providing a high performance data path between IDE devices and the PCI bus. Four IDE chip select signals provide accessing of up to four devices. Each device has W83C554F own programmable registers for selecting 16-bit and 32-bit data pipelined transfer rates, read-ahead and posted writes. A large 64 Byte DMA FIFO buffers data to and from the IDE disks enabling the integrated scatter/gather DMA controller to efficiently perform zero wait state burst transfers across the PCI bus when enough data is available in the FIFO. Bus master IDE significantly improves the overall system performance of a multi-master PCI configuration by greatly reducing the bus and CPU utilization required for the disk and CD-ROM interface. Burst data transfers at 33 MHz can be sustained at 132m MB/s on the PCI bus.

The integrated bus-mastering PCI-IDE core is the same as the W83C554F core with modification to support the new
UltraDMA/33 mode. Transfer speed on the IDE interface is up to 33MB/s. This controller is fully compliant to the SFF8038i specifications.