W971632AF

Features: · JEDEC standard 3.3V power supply· Up to 143MHz clock frequency· 262,144 words x 2 banks x 32 bits· 1 Bank Select, Row Address A0~A9, Column Address A0~A7· CAS Latency: 2 and 3· Burst Length:1, 2, 4, 8 & full page· Burst Type: Sequential & Interleave· DQM 0-3 for byte masking· A...

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W971632AF Picture
SeekIC No. : 004545341 Detail

W971632AF: Features: · JEDEC standard 3.3V power supply· Up to 143MHz clock frequency· 262,144 words x 2 banks x 32 bits· 1 Bank Select, Row Address A0~A9, Column Address A0~A7· CAS Latency: 2 and 3· Burst Len...

floor Price/Ceiling Price

Part Number:
W971632AF
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2024/2/26

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Product Details

Description



Features:

· JEDEC standard 3.3V power supply
· Up to 143MHz clock frequency
· 262,144 words x 2 banks x 32 bits
· 1 Bank Select, Row Address A0~A9, Column Address A0~A7
· CAS Latency: 2 and 3
· Burst Length:1, 2, 4, 8 & full page
· Burst Type: Sequential & Interleave
· DQM 0-3 for byte masking
· Auto & self refresh
· Write Per Bit
· 8 columns Block Write
· 32ms refresh period, 2K cycle
· LVTTL compatible interface
· 100 Pin PQFP, TQFP (14 x 20 mm)



Pinout

  Connection Diagram


Specifications

SYMBOL
ITEM
RATING
UNIT
NOTES
VIN,VOUT
VCC,VCCQ
TOPR
TSTG
TSOLDER
PD
IOS
Input/Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature(10s)
Power Dissipation
Short Circuit Output Current
-0.3~4.6
-0.3~4.6
0~70
-55~150
260
1
50
V
V
°C
°C
°C
W
mA
1
1
1
1
1
1
1



Description

W971632AF is a 16,777216-bit synchronous graphic memory organized as 262,144 words x 2 banks x 32 bits. Using synchronous pipelined architecture, W971632AF delivers a data transmission rate of up to 143M words per second.

Accesses to the SGRAM W971632AF are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SGRAM W971632AF internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. Using a pogrammable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance.

With write-per-bit and block-write functions, W971632AF is optimized for graphics drawing operation.




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