W9816G6BB

Features: • 2.7V − 3.6V power supply• Up to 200 MHz clock frequency• 524,288 words x 2 banks x 16 bits organization• Self Refresh Current: standard and low power• CAS latency: 2 and 3• Burst length: 1, 2, 4, 8, and full page• Burst read, single write...

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W9816G6BB Picture
SeekIC No. : 004545349 Detail

W9816G6BB: Features: • 2.7V − 3.6V power supply• Up to 200 MHz clock frequency• 524,288 words x 2 banks x 16 bits organization• Self Refresh Current: standard and low power•...

floor Price/Ceiling Price

Part Number:
W9816G6BB
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

• 2.7V − 3.6V power supply
• Up to 200 MHz clock frequency
• 524,288 words x 2 banks x 16 bits organization
• Self Refresh Current: standard and low power
• CAS latency: 2 and 3
• Burst length: 1, 2, 4, 8, and full page
• Burst read, single write mode
• Byte data controlled by UDQM and LDQM
• Auto-precharge and controlled precharge
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Package: BGA 60 balls pitch = 0.65 mm using
PB free materials



Specifications

ITEM SYMBOL
RATING
UNIT
NOTES
Input, Output Voltage VIN,VOUT
-0.3 - 4.6
V
1
Power Supply Voltage VDD, VDDQ
-0.3~4.6
V
1
Operating Temperature TOPR
0~70
°C
1
Storage Temperature TSTG
-55~150
°C
1
Soldering Temperature(10s) TSOLDER
260
°C
1
Power Dissipation PD
1
W
1
Short Circuit Output Current IOUT
50
mA
1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.


Description

W9816G6BB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 2 banks x 16 bits. Using pipelined architecture and 0.175 m process technology, W9816G6BB delivers a data bandwidth of up to 286M bytes per second (-7).

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing W9816G6BB address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9816G6BB is ideal for main memory in high performance applications.




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