W982504BH

Features: · CAS latency: 2 and 3· Burst Length: 1, 2, 4, 8, and full page· Burst read, Single Writes Mode· Byte data controlled by DQM· Power-Down Mode· Auto-Precharge and controlled precharge· 4K refresh cycles / 64ms· Interface: LVTTL· Package: TSOP II 54 pin, 400 mil - 0.80 PinoutSpecifications...

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W982504BH Picture
SeekIC No. : 004545352 Detail

W982504BH: Features: · CAS latency: 2 and 3· Burst Length: 1, 2, 4, 8, and full page· Burst read, Single Writes Mode· Byte data controlled by DQM· Power-Down Mode· Auto-Precharge and controlled precharge· 4K r...

floor Price/Ceiling Price

Part Number:
W982504BH
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

·  CAS latency: 2 and 3
·  Burst Length: 1, 2, 4, 8, and full page
·  Burst read, Single Writes Mode
·  Byte data controlled by DQM
·  Power-Down Mode
·  Auto-Precharge and controlled precharge
·  4K refresh cycles / 64ms
·  Interface: LVTTL
·  Package: TSOP II 54 pin, 400 mil - 0.80 



Pinout

  Connection Diagram


Specifications

SYMBOL

ITEM

RATING

UNIT

NOTES

VIN,VOUT

Input, Output Voltage

-0.3~VCC+0.3

V

1

VCC,VCCQ

Power Supply Voltage

-0.3~4.6

V

1

TOPR

Operating Temperature

0~70

°C

1

TSTG

Storage Temperature

-55~150

°C

1

TSOLDER

Soldering Temperature(10s)

260

°C

1

PD

Power Dissipation

1

W

1

IOUT

Short Circuit Output Current

50

mA

1




Description

W982504BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 8M words x 4 banks x 4 bits. Using pipelined architecture and 0.20um process technology, W982504BH delivers a data bandwidth of up to 133M (-75) words per second. To fully comply with the personal computer industrial standard, W982504BH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification. The -8H is compliant to the PC100/CL2 specification.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing W982504BH's address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W982504BH is ideal for main memory in high performance applications.




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