WCSN0436V1P

The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The WCSN0436V1P is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.The WCSN0436V1P is pin/functionally compatible to ZBT SRAMsIDT71V546, MT55L128L36P, and MCM63Z736.

All synchronous inputs of WCSN0436V1P pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The  clock input of WCSN0436V1P is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.5 ns (166-MHz device).

Write operations of WCSN0436V1P are controlled by the four Byte Write Select (BWS_[3:0] ) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output  WCSN0436V1P drivers are synchronously three-stated during the data portion of a write sequence.