WD76C20

The WD76C20 is designed with Western Digital's 1.25 micron CMOS process. It is available in 84-lead PLCC and POFP packages.On the disk drive interface, the FDC includes data separation and write precompensation in addition to the usual formatting, encoding/decoding, stepper motor control and status sensing functions.All inputs are TTL compatible, and outputs are high-current, open-drain drivers meeting the ANSI specification of 48 mA.

Features of the WD76C20 are:(1)84-pin PLCC and PQFP packages; (2)5V only supply requirement; (3)3.0V battery backup supply for the RTC and 114 byte SRAM; (4)implemented in a low-power, high performance CMOS technology; (5)12 or 24 hour clock with AM and PM in 12-hour mode; (6)daylight savings time option; (7)automatic leap year compensation; (8)interfaced with sofware as 128 RAM locations; (9)114 bytes of general purpose RAM; (10)status bit indicates data integrity; (11)bus compatible interrupt signals(IRQ).This section contains a general architectural overview of the WD76C20 which provides a costeffective, power-efficient solution to PC systems design problems, especially those relating to "lap-top" devices.The section also  illustrates the WD76C20's packaging and includes a listing of pin numbers with associated signal mnemonics and functions.

The absolute maximum ratings of the WD76C20 can be summarized as:(1)voltage at any pin:+0.3V;(2)storage temperature:-55 to 150;(3)Vcc:7.0V;(4)temperature under bias:0 to 70.The Bus Interface Logic (BIL) section of the WD76C20 provides the DB7 multiplexing necessary to implement a PC/AT compatible IDE drive interface and the Chip Select Logic section incorporates miscellaneous chip selects and control strobes necessary for the implementation of a PC/AT compatible system. The Suspend/Resume section supports the chip set power down mode by providing a 14.318 MHz clock during Resume and a 32.768 KHz clock during Suspend mode.An external DRAM refresh signal is also provided by the Suspend/Resume section to support the chip set.Traditionally, data rate selection, drive selection,and motor control have been output ports of the host processor architecture.  In the PC AT, these functions were latched into registers addressed within the I/O mapping of the system.These registers, Operations and Control, are incorporated into the FDC.