WED416S8030A-SI

Features: · Single 3.3V power supply· Fully Synchronous to positive Clock Edge· SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)· Burst Operation• Sequential or Interleave• Burst length = programmable 1,2,4,8 or full page• Burst Read and Write• Multiple Burst Read and Single Wr...

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SeekIC No. : 004545588 Detail

WED416S8030A-SI: Features: · Single 3.3V power supply· Fully Synchronous to positive Clock Edge· SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)· Burst Operation• Sequential or Interleave• Burst length = pr...

floor Price/Ceiling Price

Part Number:
WED416S8030A-SI
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/3

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Product Details

Description



Features:

· Single 3.3V power supply
· Fully Synchronous to positive Clock Edge
· SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)
· Burst Operation
• Sequential or Interleave
• Burst length = programmable 1,2,4,8 or full page
• Burst Read and Write
• Multiple Burst Read and Single Write
· DATA Mask Control per byte
· Auto Refresh (CBR) and Self Refresh
• 4096 refresh cycles across 64ms
· Automatic and Controlled Precharge Commands
· Suspend Mode and Power Down Mode



Pinout

  Connection Diagram


Specifications

Parameter Symbol Min Max Unit
Power Supply Voltage VCC -1.0 +4.6 V
Input Voltage VIN -1.0 +4.6 V
Output Voltage VOUT -1.0 +4.6 V
Operating Temperature TOPR -40 +85
Storage Temperature TSTG -55 +125
Power Disspation PD   1.0 W
Short Circuit Output Current IOS   50 mA

Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The WED416S8030A-SI is 134,217,728 bits of synchronous high data rate DRAM organized as 4 x  2,097, 152 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Available in a 54 pin TSOP type II package the WED416S8030A-SI is tested over the industrial temp range (-40°C to +85°C) providing a solution for rugged main memory applications.




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