WM8805

Features: • S/PDIF (IEC60958-3) compliant.• Advanced jitter attenuating PLL with low intrinsic period jitter of 50 ps RMS.• S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation.• Supports 10 27MHz crystal clock frequencies.• 2-wire / 3-Wi...

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SeekIC No. : 004546219 Detail

WM8805: Features: • S/PDIF (IEC60958-3) compliant.• Advanced jitter attenuating PLL with low intrinsic period jitter of 50 ps RMS.• S/PDIF recovered clock using PLL, or stand alone crystal...

floor Price/Ceiling Price

Part Number:
WM8805
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/18

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Product Details

Description



Features:

• S/PDIF (IEC60958-3) compliant.
• Advanced jitter attenuating PLL with low intrinsic period jitter of 50 ps RMS.
• S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation.
• Supports 10 27MHz crystal clock frequencies.
• 2-wire / 3-Wire serial or hardware control interface.
• Programmable Audio data interface modes:
- I2S, Left, Right Justified or DSP
- 16/20/24 bit word lengths
• 8 channel receiver input and 1 channel transmit output.
• Auto frequency detection / synchronisation.
• Selectable output status data bits.
• Up to 8 configurable GPO pins.
• De-emphasis flag output.
• Non-audio detection including DOLBYTM and DTSTM.
• Channel status changed flag.
• Configurable clock distribution with selectable output MCLK rate of 512fs, 256fs, 128fs and 64fs.
• 2.7 to 3.6V digital and PLL supply voltages.
• 28-lead SSOP package.



Application

• Surround Sound AV processors and Hi-Fi systems
• Music industry applications
• DVD-P/DVD-RW
• Digital TV



Pinout

  Connection Diagram


Specifications

CONDITION MIN MAX
Digital core and I/O buffer supply voltage -0.3V +5V
PLL supply voltage -0.3V +5V
Voltage range digital inputs DGND -0.3V DVDD +0.3V
Master Clock Frequency   37MHz
Operating temperature range, TA -25°C +85°C
Storage temperature -65°C +150°C
Note:
1. PLL and digital supplies must always be within 0.3V of each other.
2. PLL and digital grounds must always be within 0.3V of each other.



Description

The WM8805 is a high performance consumer mode S/PDIF transceiver with support for 8 received Channels and 1 transmitted Channel.

A crystal derived, or externally provided high quality master clock is used to allow low jitter recovery of S/PDIF supplied master clocks.

Generation of all typically used audio clocks is possible using the high performance internal PLL. A dedicated CLKOUT pin provides a high drive clock output.

A pass through option of WM8805  is provided which allows the device simply to be used to clean up (de-jitter) the received digital audio signals.

The WM8805 may be used under software control or stand alone hardware control modes. In software control mode, both 2-wire with read back and 3-wire interface modes are supported.

Status and error monitoring is built-in and results can be read back over the control interface, on the GPO pins or streamed over the audio data interface in 'With Flags' mode (audio data with status flags appended).

The audio data interface supports I2S, left justified, right justified and DSP audio formats of 16-24 bit word length, with sample rates from 32 to 192ks/s.

The WM8805 is supplied in a 28-lead Pb-free SSOP package.




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