XC17S10LPI

The XC17S10LPI is one member of the XC17S10 series.The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set,leveraging advanced process technologies and focusing on total cost management, the Spartan XC17S10LPI series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs.

Features of the XC17S10LPI are:(1)available in both 5V and 3.3V versions; (2)on-chip selectRAM(TM) memory; (3)fully PCI compliant; (4)full readback capability for program verification and internal node observability; (5)dedicated high-speed carry logic; (6)internal 3-state bus capability; (7)eight global low-skew clock or signal networks; (8)IEEE 1149.1-compatible Boundary Scan logic ; (9)low cost plastic packages available in all densities; (10)footprint compatibility in common packages; (11)foundation series: integrated, shrink-wrap software; (12)alliance series: dozens of PC and workstation third party development systems supported; (13)fully automatic mapping, placement and routing.

The absolute maximum ratings of the XC17S10LPI can be summarized as:(1)junction temperature:125;(2)storage temperature:-65 to 150;(3)supply voltage relative to GND:-0.5 to 7.0V;(4)supply voltage relative to GND:0.5 to +12.5 V;(5)voltage applied to 3-state output:0.5 to Vcc+0.5 V.Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability.Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.