Features: • High-Performance EPLD
7.5 ns pin-to-pin speed on all fast inputs
100 MHz maximum clock frequency
• Advanced Dual-Block architecture
Four Fast Function Blocks
Twelve High-Density Function Blocks
• 100% interconnect matrix
• High-Speed arithmetic carry network
1 ns ripple-carry delay per bit
43 MHz 16-bit accumulators
• 144 Macrocells with programmable I/O architecture
• Up to 132 inputs programmable as direct, latched, or registered
• All outputs with 24 mA drive
• 3.3 V or 5 V I/O operation
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• Power management options
• Multiple security bits for design protection
• 160-pin plastic quad flat pack and 225-pin ball-gridarray packages
• 100% PCI compliant
• Programmable slew rate
• Programmable ground controlSpecifications
| Symbol |
Parameter |
Value |
Units |
| VCC |
Supply voltage with respect to GND |
-0.5 to 7.0 |
V |
| VIN |
DC Input voltage with respect to GND |
-0.5 to VCC +0.5 |
V |
| VTS |
Voltage applied to 3-state output with respect to GND |
-0.5 to VCC +0.5 |
V |
| TSTG |
Storage temperature |
-65 to +150 |
°C |
| TSOL |
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) |
+250 |
°C |
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
DescriptionThe XC73144 is a member of the Xilinx Dual-Block EPLDfamily. It consists of four Fast Function Blocks and twelve High-Density Function Blocks interconnected by a central Universal Interconnect Matrix (UIM).
The sixteen Function Blocks in the XC73144 are PAL-like structures, complete with programmable product term arrays and programmable multilevel Macrocells. Each Function Block receives 24 inputs, contains nine Macrocells configurable for registered or combinatorial logic and produces nine outputs which feedback to the UIM and output pins.
The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and interconnected without routing restrictions.
The XC73144 is designed in a 0.8 m CMOS EPROM technology. In addition, the XC73144 includes a programmable power management feature to specify high-performance or lowpower operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while noncritical paths dissipate less power.
Xilinx development software (XEPLD) supports all members of XC7300 family. The designer can create, implement, and verify digital logic circuits for EPLD devices using the Xilinx XEPLD Development System. Designs can be represented as schematics consisting of XEPLD library components, as behavioral descriptions, or as a mixture of both. The XEPLD translator automatically performs logic optimization, collapsing, mapping and routing without user intervention. After compiling the design, XEPLD translator produces documentation for design analysis and creates a programming file to configure the device.
The following lists some of the XEPLD Development System features.
• Familiar design approach similar to TTL and PLD techniques
• Converts netlist to fuse map in minutes using a 386/486 PC or workstation platform
• Interfaces to standard third-party CAE schematics, simulation tools, and behavioral languages
• Timing simulation using Viewsim, OrCAD VST, Mentor, LMC and other tools compatible with the Xilinx Netlist Format (XNF)
XC73144 Data Sheet
