XCR3032C

Features: • Industry's first TotalCMOS™ PLD - both CMOS design and process technologies• Fast Zero Power (FZP™ design technique provides ultra-low power and very high speed• High speed pin-to-pin delays of 8 ns• Ultra-low static power of less than 35 µA...

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XCR3032C: Features: • Industry's first TotalCMOS™ PLD - both CMOS design and process technologies• Fast Zero Power (FZP™ design technique provides ultra-low power and very high speed&#...

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Part Number:
XCR3032C
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2021/1/17

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Product Details

Description



Features:

• Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
• Fast Zero Power (FZP™ design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 8 ns
• Ultra-low static power of less than 35 µA
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• Up to six clocks available
• Programmable clock polarity at every macrocell
• 3.3V, In-System Programmable (ISP) using a JTAG interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program, Verify
- Supported by multiple ISP programming platforms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Xilinx CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two asynchronous clocks
• Programmable global 3-state pin facilitates `bed of nails' testing without using logic resources
• Available in both PLCC and VQFP packages



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Min
Max.
Unit
VCC
Supply voltage2
-0.5
7.0
V
VI
Input voltage
-1.2
VCC + 0.5
V
VOUT
Output voltage
-0.5
VCC +0.5
V
IIN
Input current
-30
30
mA
IOUT
Output current
-100
100
mA
TJ
Maximum junction temperature
-40
150
°C
Tstr
Storage temperature
-65
150
°C



Description

The XCR3032C CPLD (Complex Programmable Logic Device) is a member of the CoolRunner ® family of CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design tech-nique, the XCR3032C offers true pin-to-pin speeds of 8 ns, while simultaneously delivering power that is less than 35 µA at standby without the need for  "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a tech- nique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology  and the pat- ented full CMOS FZP design technique. For 5V applica- tions, Xilinx also offers the high speed XCR5032C CPLD that offers pin-to-pin speeds of 6 ns.

The Xilinx FZP XCR3032C CPLDs utilize the patented XPLA (extended Programmable Logic Array) architecture. The XPLA archi- tecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allo-  cation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 8 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently through-  out the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which  results  in
worst case tPD's of only 10.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.

The XCR3032C CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design ver- ification uses industry standard simulators for functional and timing simulation. Development is supported on per- sonal computer, Sparc, and HP platforms. Device fitting




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