Features: - Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture - Reset controller - IEEE 1149.1 test access port (JTAG)• Interrupts - Seven external interrupt request (IRQ) lines - 12 port pins with interrupt capability - 23 internal interrupt sources -...
XPC855TCZP50D4: Features: - Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture - Reset controller - IEEE 1149.1 test access port (JTAG)• Interrupts - Seven external interru...
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- Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
- Reset controller
- IEEE 1149.1 test access port (JTAG)
• Interrupts
- Seven external interrupt request (IRQ) lines
- 12 port pins with interrupt capability
- 23 internal interrupt sources
- Programmable priority between SCCs
- Programmable highest priority request
• 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using ATM over UTOPIA interface)
• ATM support compliant with ATM forum UNI 4.0 specification
- Cell processing up to 5070 Mbps at 50-MHz system clock
- Cell multiplexing/demultiplexing
- Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software implementation of other protocols).
- ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and unspecified bit rate (UBR) and providing control mechanisms enabling software support of available bit rate (ABR)
- Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and byte-aligned serial (for example, T1/E1/ADSL)
- UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to 4 physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or 1/3.
- Serial-mode ATM connection supports transmission convergence (TC) function for T1/E1/ADSL lines; cell delineation; cell payload scrambling/descrambling; automatic idle/unassigned cell insertion/stripping; header error control (HEC) generation, checking, and statistics.
• Communications processor module (CPM)
- RISC communications processor (CP)
- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT ENTER HUNT MODE , and RESTART TRANSMIT)
- Supports continuous mode transmission and reception on all serial channels
- Up to 8Kbytes of dual-port RAM
- 16 serial DMA (SDMA) channels- Three parallel I/O registers with open-drain capability
• Four baud-rate generators (BRGs)
- Independent (can be connected to any SCC or SMC)
- Allow changes during operation
- Autobaud support option
• Four serial communications controllers (SCCs)
- Ethernet/IEEE 802.3 optional on SCC14, supporting full 10-Mbps operation (available only on specially programmed devices).
- HDLC/SDLC (all channels supported at 2 Mbps)
- HDLC bus (implements an HDLC-based local area network (LAN))
- Asynchronous HDLC to support PPP (point-to-point protocol)
- AppleTalk
- Universal asynchronous receiver transmitter (UART)
- Synchronous UART
- Serial infrared (IrDA)
- Binary synchronous communication (BISYNC)
- Totally transparent (bit streams)
- Totally transparent (frame based with optional cyclic redundancy check (CRC))
• Two SMCs (serial management channels)
- UART
- Transparent
- General circuit interface (GCI) controller
- Can be connected to the time-division multiplexed (TDM) channels
• One SPI (serial peripheral interface)
- Supports master and slave modes
- Supports multimaster operation on the same bus
• One I2 C (inter-integrated circuit) port
- Supports master and slave modes
- Multiple-master environment support
• Time-slot assigner (TSA)
- Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
- 1- or 8-bit resolution
Rating | Symbol | Value | Unit |
Supply Voltage1 | VDDH | 0.3 to 4.0 | V |
VDDL | 0.3 to 4.0 | V | |
KAPWR | 0.3 to 4.0 | V | |
VDDSYN | 0.3 to 4.0 | V | |
Input Voltage2 | Vin | GND 0.3 to VDDH | V |
Temperature3(Standard) | TA(min) | 0 | |
Tj(max) | 95 | ||
Temperature3(Extended) | TA(min) | 40 | |
Tj(max) | 95 | ||
Storage Temperature Range | Tstg | 55 to 150 |
1 The power supply of the device must start its ramp from 0.0 V.
2 Functional operating conditions are provided with the DC electrical specifications in Table 6-5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. Caution : All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be applied to its inputs).
3Minimum temperatures are guaranteed as ambient temperature, TA . Maximum temperatures are guaranteed as junction temperature, Tj