XPS 16550 UART

Features: • PLB v4.6 based PLB interface• Hardware and software register compatible with all standard 16450 and 16550 UARTs• Implements all standard serial interface protocols- 5, 6, 7 or 8 bits per character- Odd, Even or no parity detection and generation- 1, 1.5 or 2 stop bit ...

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SeekIC No. : 004549095 Detail

XPS 16550 UART: Features: • PLB v4.6 based PLB interface• Hardware and software register compatible with all standard 16450 and 16550 UARTs• Implements all standard serial interface protocols- 5, ...

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Part Number:
XPS 16550 UART
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• PLB v4.6 based PLB interface
• Hardware and software register compatible with all standard 16450 and 16550 UARTs
• Implements all standard serial interface protocols
- 5, 6, 7 or 8 bits per character
- Odd, Even or no parity detection and generation
- 1, 1.5 or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver clock input
- Modem control functions
- Prioritized transmit, receive, line status and modem control interrupts
- False start bit detection and recover
- Line break detection and generation
- Internal loop back diagnostic functionality
- Independent 16 word transmit and receive FIFOs




Application

The use of the XPS 16550 UART in 16550 mode is outlined in the steps below.

1. The system programmer specifies the format of the asynchronous data communications exchange i.e Data bits (5,6,7 or 8), setting of parity ON and selecting on the even or odd parity, setting of the number stop bits for the transmission and set the Divisor latch access bit by programming the Line Control Register.
2. Write Interrupt Enable Register to activate the individual interrupts
3. Write to the FIFO Control Register to enable the FIFO's, clear the FIFO's, set the RCVR FIFO trigger level.
4. Write to Divisor Latch least significant byte first and Divisor Latch most significant byte second for proper setting of the baud rate of the UART.
5. Service the interrupts when ever an interrupt is triggered by the XPS 16550 UART. An example use of the XPS 16550 UART with the operating mode set to the following parameters in 16550 mode explained below.
- baud rate: 56Kbps
- Enabled and Threshold settings for the FIFO receive buffer.
- Format of asynchronous data exchange 8 data bits, Even parity and 2 stop bits

1. Write 0x0000_0080 to Line Control Register.This configures DLAB bit which allows the writing into the Divisor Latch's Least significant and Most significant bytes.

2. Write 0x0000_0002 to Divisor Latch's Least significant byte and write 0x0000_0000 to Divisor Latch's Most significant byte in that order. This configures the baud rate setup of UART to 56Kbps operation.

3. Write 0x0000_001F to Line Control Register. This configures word length to 8 bits, Number of stop bits to 2, Parity is enabled and set to Even parity and DLAB bit is set to value 0 to enable the use of Transmit Holding register and Receive buffer register data for transmitting and reception of data.

4. Write 0x0000_0011 to Interrupt Enable Register. This enables the Transmitter holding register empty interrupt and Receive data available interrupt.

5. Write the buffer to Transmit Holding register and read the data received from Receive Holding register by servicing the interrupts generated.




Description

The XPS 16550 UART implements the hardware and software functionality of the ubiquitous National Semiconductor 16550 UART, that works in both 16450 and 16550 UART modes. For complete details please refer the National Semiconductor data sheet.

The XPS 16550 UART performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion on characters received from a modem or microprocessor peripheral.

The XPS 16550 UART is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or 1 stop bits and odd, even or no parity. The XPS 16550 UART can transmit and receive independently.

The device can be configured and it's status monitored via the internal register set. The XPS 16550 UART is capable of signaling receiver, transmitter and modem control interrupts. These interrupts can be masked, are prioritized and can be identified by reading an internal register.

The XPS 16550 UART contains a 16 bit, programmable, baud rate generator and independent 16 word transmit and receive FIFOs. The FIFOs can be enabled or disabled through software control.

The top-level block diagram for the XPS 16550 UART is shown in Figure 1.




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