XQ18V04

Xilinx introduces the QPro™ XQ18V04 and XQR18V04 series of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams.

When the XQ18V04 is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.

When the XQ18V04 is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins.

The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 6.