Features: Fully Integrated 2.048Mbits/s Line Interface Intended For Use In Systems That Must Comply With CCITT Specifications G.703, G.823, I.431, G.732, G.735, G.739 Pin-Selectable 75W or 120W Operation Monolithic Clock Recovery Low Power Dissipation:100mW for 120W Twisted Pair, Typical108mW for...
XR-T7288: Features: Fully Integrated 2.048Mbits/s Line Interface Intended For Use In Systems That Must Comply With CCITT Specifications G.703, G.823, I.431, G.732, G.735, G.739 Pin-Selectable 75W or 120W Ope...
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DC Supply Voltage (VDD) . . . . . . . . . . . -0.5V to +6.5V
Power Dissipation (Pdis) . . . . . . . . . . . . . . . . . 500mW
Storage Temperature (Tstg) . . . . . . . -65 to +125
Maximum Voltage (any pin) with Respect
to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Minimum Voltage (any pin) with Respect to GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V
Maximum Allowable Voltages
(T1, R1) with Respect to GND . . . . . . -5.0V to 5.0V
Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to Absolute Maximum Ratings for extended periods can adversely affect device reliability. pin assignment ordering information
The XR-T7288 CEPT1 Line Interface is an integrated circuit that provides a 2.048 Mbits/s line interface to either twisted-pair or coaxial cable as specified in CCITT requirements G.703, G.823, I.431, G.732, and G.735 G.739. The device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. The XR-T7288 device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package for surface mounting.
The XR-T7288 device is functionally compatible with the LC1135B device. The digital circuitry is shown in Figure 1.; the analog circuitry is shown in Figure 6.