XRK32308

XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FB pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. XRK32308 has two banks of four outputs each.

These can be controlled by the Select inputs as shown in Table 2, "Select Input Decoding," on page 2.

If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes.

Multiple XRK32308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

XRK32308 devices are available in five different configurations, as shown in Table 3, "Available XRK32308 Configurations," on page 3.

The XRK323081 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path.