XRT7300

` Meets E3/DS3/STS-1 Jitter Tolerance Require-ments
` Full Loop-Back Capability
` Transmit and Receive Power Down Modes
` Full Redundancy Support
` Contains a 4-Wire Microprocessor Serial Interface
` Uses Minimum External components
` Requires Single +5V Power Supply
` -40 to +85 Operating Temperature Range
` Available in a 44 pin TQFP package

· Interfaces to E3, DS3 or SONET STS-1 Networks
· CSU/DSU Equipment
· PCM Test Equipment
· Fiber Optic Terminals
· Multiplexers

Figure 5 presents the test circuit that was used to test Figure 6, Figure 7 and Figure 8 present the Pulseand measure the pulse amplitudes as listed in the Template requirements for the E3, DS3 and STS-1 ELECTRICAL CHARACTERISTICS tables. Rates.

Exar's XRT7300 DS3/E3/STS-1 transceiver is an integrated solution which combines and enhances the present XRT7295/XRT7298 two-chip solution. The device contains both the receiver and transmitter to support the data rates at DS3 (44.736Mbps), E3 (34.368Mbps) or STS-1 (51.84Mbps).

The XRT7300 is a full featured Line Interface Unit (LIU). In the transmit direction, it accepts digital clock and data from the terminal equipment, usually a TDM framer (XRT7250), or an ATM UNI (XRT7234/XRT7245). It optionally encodes the data, and converts it into the appropriate pulse shapes for transmission over coaxial cable. In the receive direction, it accepts a bipolar signal from the line, optionally performs equalization, converts the line signal into a dual rail binary data stream, recovers the clock, optionally decodes the data, and coverts it into a dual rail digital signal.

The XRT7300 transceiver has several key features. It is compliant with all applicable ITU-I, ANSI, and Bellcore standards including, but not limited to, ITU-T G.775, G.823_1993, G.824, Bellcore TR-NWT-000499, and ANSI T1.404. Apart from the standard features such as built-in B3ZS/HDB3 encoder/decoder, and pulse shaping circuitry, the XRT7300 transceiver offers a fully integrated clock recovery circuit.

Additionally, it incorporates an on-chip transmit clock duty-cycle correction circuit to guarantee pulse template compliance without the need for a tightly controlled transmit clock (similar feature to XRT7298). It supports error detection and declaration (in compliance with G.775) for Loss of Signal (LOS), Loss of Lock (LOL), and Line Code Violations (LCV). It supports either transformer coupling or capacitive coupling to the receiver line interface.

When transformer coupling is used, the XRT7300 transceiver operates with a less expensive, and more stable (over temperature), 1:1 transformer for both transmit and receive line connections. The XRT7300 transceiver can be operated in either a hardware mode or host mode. The XRT7300 transceiver can be configured (through either external signals or microprocessor interface) to any of the three data rates WITHOUT changing any external components.

The XRT7300 is aimed at telecommunications and networking equipment manufacturers supporting DS3/E3 interfaces. It is well suited for WAN networking applications such as routers and bridges, ATM switches, DSLAMs, ADMs, and DS3/E3 line cards. The XRT7300 transceiver and companions XRT7250 framer or XRT7234/45 ATM UNIs offer a single silicon source for DS3/E3 networks.