XRT91L34

Specifications Specifications DataRate(s) STS-12/3/1, STM-4/1/0 Protocols SONET/SDH Bus I/F 8-Bit TTL SystemBus I/F n/a Pwr Sup 1.8V with 3.3V I/O Pkgs LQFP-128Description The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device f...

product image

XRT91L34 Picture
SeekIC No. : 004549528 Detail

XRT91L34: Specifications Specifications DataRate(s) STS-12/3/1, STM-4/1/0 Protocols SONET/SDH Bus I/F 8-Bit TTL SystemBus I/F n/a Pwr Sup 1.8V with 3.3V I/O Pkgs LQFP-128Descripti...

floor Price/Ceiling Price

Part Number:
XRT91L34
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/4/18

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Specifications

Specifications
DataRate(s) STS-12/3/1, STM-4/1/0
Protocols SONET/SDH
Bus I/F 8-Bit TTL
SystemBus I/F n/a
Pwr Sup 1.8V with 3.3V I/O
Pkgs LQFP-128





Description



The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The device internally monitors Loss of Lock (LOL) conditions and automatically mutes recovered data upon Loss of Signal (LOS) conditions.

Clock and Data Recovery Overview

The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the LVDS or Differential LVPECL receiver and generates a clock that is the same frequency as the incoming data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. All four channels share a single 77.76MHz or 19.44MHz reference clock. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock.

Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/mapper device. When the SDEXT is de-asserted by the optical module or when internal DLOS is asserted, the receive serial data output will be forced to a logic zero state for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the SDEXT becomes active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.






Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Potentiometers, Variable Resistors
Audio Products
Resistors
Crystals and Oscillators
View more