XRT91L82

Features: · 2.488 / 2.666 Gbps Transceiver· Targeted for SONET OC-48/SDH STM-16 Applications· Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps· Single-chip fully integrated solution containing parallel-to-serial converter, clock mu...

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SeekIC No. : 004549531 Detail

XRT91L82: Features: · 2.488 / 2.666 Gbps Transceiver· Targeted for SONET OC-48/SDH STM-16 Applications· Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of...

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Part Number:
XRT91L82
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

· 2.488 / 2.666 Gbps Transceiver
· Targeted for SONET OC-48/SDH STM-16 Applications
· Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps
· Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto- parallel converter, and clock data recovery (CDR) functions
· 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL signaling data paths running at 155.52/166.63 Mbps using internal input termination for reduced passive components on board
· Non-FEC and FEC rate REF1CLKP/N and REF2CLKP/N dual reference input ports
· Supports 155.52/166.63MHz or 77.76/83.31MHz transmit and receive external reference input ports
· Optional VCXO input port support multiple de-jittering modes in Host mode
· On-chip phase detector and charge pump for external VCXO based de-jittering PLL
· Internal FIFO decouples transmit parallel clock input and transmit parallel clock output
· Provides Local, Remote Serial and Remote Parallel Loopback modes as well as Loop Timing mode
· Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect
· Host mode serial microprocessor interface simplifies monitor and control
· Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, GR-253 CORE, GR-253-ILR- SONET Jitter specifications.
· Operates at 1.8V CMOS and CML Power with 3.3V I/O
· 500mW Typical Power Dissipation using LVDS Interface
· Package: 15 x 15 mm 196-pin STBGA
· IEEE 1149.1 Compatable JTAG port





Application

· SONET/SDH-based Transmission Systems
· Add/Drop Multiplexers
· Cross Connect Equipment
· ATM and Multi-Service Switches, Routers and Switch/Routers
· DSLAMS
· SONET/SDH Test Equipment
· DWDM Termination Equipment





Specifications

Specifications
DataRate(s) 1xOC-48, 1xSTM-16
Protocols SONET/SDH
Bus I/F LVDS
SystemBus I/F n/a
Pwr Sup 1.8V with 3.3V I/O
Pkgs STBGA-196


Thermal Resistance of STBGA Package....QjA = 25°C/W
Operating Temperature Range .................-40°C t o 85°C
Thermal Resistance of STBGA Package ....QjC = 10°C/W
Case Temperature under bias..................-55°C to 125°C
ESD Protection (HBM) ..........................................>2000V
Storage Temperature ...............................-65°C to 150°C






Description

Description

The XRT91L82 is a fully integrated SONET/SDHtransceiver for OC-48/STM16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel andparallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the controlof the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in looptiming mode to clean up the recovered clock in the receive section.



The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase- Locked Loop (PLL) to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions.

The transmit section includes a 16x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the FIFO_AUTORST register bit can automaticallyrecover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section.






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