Z550

Features: • Full double buffering• Full status reporting• 16 byte receive and transmit FIFOs reduce CPU interrupts• Independent control of transmit, receive, line status data set interrupts and FIFOs• Modem control signals include: CTS, DCD, DSR, DTR, RI, RTS• P...

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SeekIC No. : 004550216 Detail

Z550: Features: • Full double buffering• Full status reporting• 16 byte receive and transmit FIFOs reduce CPU interrupts• Independent control of transmit, receive, line status data...

floor Price/Ceiling Price

Part Number:
Z550
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

• Full double buffering
• Full status reporting
• 16 byte receive and transmit FIFOs reduce CPU interrupts
• Independent control of transmit, receive, line status data set interrupts and FIFOs
• Modem control signals include: CTS, DCD, DSR, DTR, RI, RTS
• Programmable serial interface characteristics: - 5, 6, 7, or 8 bit characters
- odd, even, or no parity generation and detection
- 1, 1.5, or 2 stop bits
• Programmable Baud Rate Generator (dc to 56k baud)
• Unique OKI methodology for input timing analysis
• Tailored design flow and test procedure alleviates user from test vector generation to verify Z550 functionality
• Specially developed software merges OKI test vectors with the user's circuit



Pinout

  Connection Diagram


Description

The Z550 UART Mega Macrocell is a featured library element in all of OKI's 0.5 m Sea of Gates and 0.5 m Customer Structured Array families. The OKI implementation of the mega macrocell is fully compatible with industry standard 16550 functions.

The Z550 UART Mega Macrocell is an Asynchronous Communication Element (ACE), functionally equivalent to the industry standard 16550 with 16 byte FIFOs available on both the transmitter and receiver. It serves as a serial I/O interface in microcomputer systems performing serial to parallel conversions on data characters received from peripheral devices or modems and parallel to serial conversions on data characters transmitted by the CPU. In FIFO mode, the FIFOs are enabled allowing 16 bytes of data to be stored during both transmit and receive operations. The receive FIFO also provides three bits per byte of error data. The status of the ACE can be read at any time by the CPU. Available information includes the type and condition of transfer operations being performed and error conditions involving parity, overrun, framing or break interrupt. The ACE includes a built in baud rate generator with 18 programmable baud rates.




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