HD6483687G

Features:

•High-speed H8/300H central processing unit with an internal 16-bit architecture
  Upward-compatible with H8/300 CPU on an object level
  Sixteen 16-bit general registers
  62 basic instructions
•Various peripheral functions
  RTC (can be used as a free running counter)
  Timer B1 (8-bit timer)Timer V (8-bit timer)
  Timer Z (16-bit timer)
  14-bit PWM
  Watchdog timer
  SCI (Asynchronous or clocked synchronous serial communication interface) × 2 channels
  I2C Bus Interface (conforms to the I2C bus interface format that is advocated by PhilipsElectronics)
  10-bit A/D converter 


Application

•Interrupt edge select register 1 (IEGR1)
•Interrupt edge select register 2 (IEGR2)
•Interrupt enable register 1 (IENR1)
•Interrupt enable register 2 (IENR2)
•Interrupt flag register 1 (IRR1)
•Interrupt flag register 2 (IRR2)
•Wakeup interrupt flag register (IWPR)


Pinout




Description

The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes.

Arithmetic and logic instructions can use the H8/300H register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.