SN54AS869

These synchronous, presettable, 8-bit up/down counters SN54AS869 feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP</a>, ENT</a>) inputs and internal gating. This SN54AS869 of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.

These counters SN54AS869 are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs of SN54AS869 to agree with the data inputs after the next clock pulse.

The carry look-ahead circuitry of SN54AS869 provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (ENP</a> and ENT</a>) inputs and a ripple-carry (RCO</a>) output are instrumental in accomplishing this function. Both ENP</a> and ENT</a> must be low to count. The direction of the count SN54AS869 is determined by the levels of the select (S0, S1) inputs as shown in the function table. ENT</a> is fed forward to enable RCO</a>. RCO</a> thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse SN54AS869 can be used to enable successive cascaded stages. Transitions at ENP</a> and ENT</a> are allowed regardless of the level of CLK. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design.

These counters SN54AS869 feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the AS867 and AS869, any time ENP</a> and/or ENT</a> is taken high, RCO</a> either goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT</a>  is taken high, RCO</a> either goes or remains high. The function of the counter SN54AS869 (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.