79R3052-40MJ, 79R3052E, 79R3052E-20J Selling Leads, Datasheet
MFG:AD Package Cooled:84 PLCC D/C:2006
79R3052-40MJ, 79R3052E, 79R3052E-20J Datasheet download
Part Number: 79R3052-40MJ
MFG: AD
Package Cooled: 84 PLCC
D/C: 2006
79R3052-40MJ, 79R3052E, 79R3052E-20J
- Table of contents:
Info of 79R3052-40MJ
Info of 79R3052E
Info of 79R3052E-20J
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About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
79R3052E Maximum Ratings
| Symbol | Rating | Commercial | Unit |
| VTERM | Terminal Voltage with Respect to GND |
0.5 to +7.0 | V |
| TC | Operating Case Temperature |
0 to +85 | |
| TBIAS | Case Temperature Under Bias |
55 to +125 | |
| TSTG | Storage Temperature |
55 to +125 | |
| VIN | Input Voltage | 0.5 to +7.0 | V |
79R3052E Features
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
- IDT79R3000A /IDT79R3001 RISC Integer CPU
- R3051 features 4KB of Instruction Cache
- R3052 features 8KB of Instruction Cache
- All devices feature 2kB of Data Cache
- "E" Versions (Extended Architecture) feature full
function Memory Management Unit, including 64-
entry Translation Lookaside Buffer (TLB)
- 4-deep write buffer eliminates memory write stalls
- 4-deep read buffer supports burst refill from slow
memory devices
- On-chip DMA arbiter
- Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging that's pin-/packagecompatible
with thermally enhanced 84-pin MQUAD.
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
- Optimizing compilers
- Real-time operating systems
- Monitors/debuggers
- Floating Point Software
- Page Description Languages
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
- IDT79R3000A /IDT79R3001 RISC Integer CPU
- R3051 features 4KB of Instruction Cache
- R3052 features 8KB of Instruction Cache
- All devices feature 2kB of Data Cache
- "E" Versions (Extended Architecture) feature full
function Memory Management Unit, including 64-
entry Translation Lookaside Buffer (TLB)
- 4-deep write buffer eliminates memory write stalls
- 4-deep read buffer supports burst refill from slow
memory devices
- On-chip DMA arbiter
- Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging that's pin-/packagecompatible
with thermally enhanced 84-pin MQUAD.
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
- Optimizing compilers
- Real-time operating systems
- Monitors/debuggers
- Floating Point Software
- Page Description Languages
79R3052E Connection Diagram
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