79RC32351

Features:

RC32300 32-bit Microprocessor
  Enhanced MIPS-II ISA
  Enhanced MIPS-IV cache prefetch instruction
  DSP Instructions
  MMU with 16-entry TLB
  8kB Instruction cache, 2-way set associative
  2kB Data cache, 2-way set associative
  Per line cache locking
  Write-through and write-back cache management
  Debug interface through the EJTAG port
  Big or little endian support
Interrupt Controller
  Allows status of each interrupt to be read and masked
UARTs
  Two 16550 Compatible UARTs
  Baud rate support up to 1.5 Mb/s
Counter/Timers
  Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
  32 individually programmable pins:
    each pin programmable as input, output, or alternate function,
    input can be an interrupt or NMI source,
    input can also be active high or active low
  4 additional, auxiliary GPIO pins can be configured as input or output
SDRAM Controller
  2 memory banks, non-interleaved, 512 MB total
  32-bit wide data path
  Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
  SODIMM support
  Stays on page between transfers
  Automatic refresh generation
Peripheral Device Controller
  26-bit address bus
  32-bit data bus with variable width support of 8-,16-, or 32-bits
  8-bit boot ROM support
  6 banks available, up to 64MB per bank
  Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices
  Supports external wait-state generation, Intel or Motorola style
  Write protect capability
  Direct control of optional external data transceivers
System Integrity
  Programmable system watchdog timer resets system on timeout
  Programmable bus transaction times memory and peripheral
    transactions and generates a warm reset on time-out
DMA
  14 DMA channels
  Services on-chip and external peripherals
  Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O transfers
  Supports flexible descriptor based operation and chaining via
    linked lists of records (scatter / gather capability)
  Supports unaligned transfers


Specifications

Symbol	Parameter	Min1	Max1	Unit
VCCI/O	I/O Supply Voltage	-0.6	4.0	V
VCCCore	Core Supply Voltage	-0.3	3.0	V
VCCP	PLL Supply Voltage	-0.3	3.0	V
Vimin	Input Voltage - undershoot	-0.6	-	V
Vi	I/O Input Voltage	Gnd	VCCI/O+0.5	V
Ta, Industrial	Ambient Operating Temperature	0	70	degrees C
Tstg	Storage Temperature	-40	125	degrees C

1. Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability
or cause permanent damage to the device.


Description

The following table lists the functions of the pins provided on the 79RC32351. Some of the functions listed may be multiplexed onto the same pin. To define the active polarity of a signal, a suffix will be used. Signals ending with an "N" should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
Note: The input pads of the 79RC32351 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
          This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32351's operation.
          Also, any input pin left floating can cause a slight increase in power consumption.