79RC32355 Selling Leads, Price trend, 79RC32355 DataSheet download, circuit diagram from SeekIC.com

Features: RC32300 32-bit Microprocessor Enhanced MIPS-II ISAEnhanced MIPS-IV cache prefetch instructionDSP InstructionsMMU with 16-entry TLB8KB Instruction Cache, 2-way set associative2KB Data Cache, 2-way set associativePer line cache lockingWrite-through and write-back cache managementDebug inte...

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SeekIC No. : 004252918 Detail

79RC32355: Features: RC32300 32-bit Microprocessor Enhanced MIPS-II ISAEnhanced MIPS-IV cache prefetch instructionDSP InstructionsMMU with 16-entry TLB8KB Instruction Cache, 2-way set associative2KB Data Cache...

79RC32355 Data Sheet

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Part Number:: 79RC32355
Supply Ability:: 5000

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1~5000

Unit Price
Negotiable

Processing time
15 Days

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Upload time: 2024/4/22

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Product Details

Description

Features:

RC32300 32-bit Microprocessor
Enhanced MIPS-II ISA
Enhanced MIPS-IV cache prefetch instruction
DSP Instructions
MMU with 16-entry TLB
8KB Instruction Cache, 2-way set associative
2KB Data Cache, 2-way set associative
Per line cache locking
Write-through and write-back cache management
Debug interface through the EJTAG port
Big or Little endian support
Interrupt Controller
Allows status of each interrupt to be read and masked
I²C
Flexible I²C standard serial interface to connect to a variety of peripherals
Standard and fast mode timing support
Configurable 7 or 10-bit addressable slave
UARTs
Two 16550 Compatible UARTs
Baud rate support up to 1.5 Mb/s
Counter/Timers
Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
36 individually programmable pins
Each pin programmable as input, output, or alternate function
Input can be an interrupt or NMI source
Input can also be active high or active low
SDRAM Controller
2 memory banks, non-interleaved, 512 MB total
32-bit wide data path
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
SODIMM support
Stays on page between transfers
Automatic refresh generation
Peripheral Device Controller
26-bit address bus
32-bit data bus with variable width support of 8-,16-, or 32-bits
8-bit boot ROM support
6 banks available, up to 64MB per bank
Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices
Supports external wait-state generation, Intel or Motorola style
Write protect capability
Direct control of optional external data transceivers
System Integrity
Programmable system watchdog timer resets system on time-out
Programmable bus transaction times memory and peripheral transactions and generates a warm reset on time-out
DMA
16 DMA channels
Services on-chip and external peripherals
Supportsmemory-to-memory,memory-to-I/O, and I/O-to-I/O transfers
Supports flexible descriptor based operation and chaining vialinked lists of records (scatter / gather capability)
Supports unaligned transfers
Supports burst transfers
USB
Revision 1.1 compliant
USB slave device controller
Supports a 6th USB endpoint
Full speed operation at 12 Mb/s
Supports control, interrupt, bulk and isochronous endpoints
Supports USB remote wakeup
Integrated USB transceiver
TDM
Serial Time Division Multiplexed (TDM) voice and data inter-face
Provides interface to telephone CODECs and DSPs
Interface to high quality audio A/Ds and D/As with external glue logic
Support 1 to 128 8-bit time slots
Compatible with Lucent CHI, GCI, Mitel ST-bus, K2 and SLD busses
Supports data rates of up to 8.192 Mb/s
Supports internal or external frame generation
Supports multiple non-contiguous active input and output time slots
EJTAG
Run-time Mode provides a standard JTAG interface
Real-Time Mode provides additional pins for real-time trace information
Ethernet
Full duplex support for 10 and 100 Mb/s Ethernet
IEEE 802.3u compatible Media Independent Interface (MII) with serial management interface
IEEE 802.3u auto-negotiation for automatic speed selection
Flexible address filtering modes
64-entry hash table based multicast address filtering
ATM SAR
Can be configured as one UTOPIA level 1 interface or 1UTOPIA level 2 interface with 2 address lines (3 PHYs max)
Supports 25Mb/s and faster ATM
Supports UTOPIA data path interface operation at speeds up to 33 MHz
Supports standard 53-byte ATM cells
Performs HEC generation and checking
Cell processing discards short cells and clips long cells
16 cells worth of buffering
UTOPIA modes: 8 cell input buffer and 8 cell output buffer
Hardware support for CRC-32 generation and checking for AAL5
Hardware support for CRC-10 generation and checking
Virtual caching receive mechanism supports reception of any length packet without CPU intervention on up to eight simulta-neously active receive channels
Frame Mode transmit mechanism supports transmission of any length packet without CPU intervention
System Features
JTAG Interface (IEEE Std. 1149.1 compatible)
208 pin PQFP package
2.5V core supply and 3.3V I/O supply
Up to 180 MHz pipeline frequency and up to 75 MHz bus frequency

Specifications

Symbol	Parameter	Min1	Max1	Unit
V_CCI/O	I/O supply Voltage	-0.3	3.465	V
V_CCCore	Core Supply Voltage	-0.3	3.0	V
V_CC^P	PLL supply	-0.3	3.0	V
Vimin	Input Voltage - undershoot	-0.6	-	V
VI	I/O Input Voltage	Gnd	V_CCI/O+ 0.6	V
Ta Industrial	Ambient Operating Temperature	-40	85	degrees C
Tstg	Storage Temperature	-40	125	degrees C

79RC32355

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