79RC32332, 79RC32333, 79RC32334 Selling Leads, Datasheet
MFG:N/A Package Cooled:N/A D/C:09+
79RC32332, 79RC32333, 79RC32334 Datasheet download
Part Number: 79RC32332
MFG: N/A
Package Cooled: N/A
D/C: 09+
79RC32332, 79RC32333, 79RC32334
- Table of contents:
Info of 79RC32332
Info of 79RC32333
Info of 79RC32334
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About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
About 79RC32333
PDF/DataSheet Download
Datasheet: 79RC32333
File Size: 426897 KB
Manufacturer: IDT
Download : Click here to Download
About 79RC32334
PDF/DataSheet Download
Datasheet: 79RC32334
File Size: 851236 KB
Manufacturer: IDT
Download : Click here to Download
79RC32332 Maximum Ratings
| Symbol | Parameter | Min1 | Max1 | Unit |
| VCC | Supply Voltage | -0.3 | 3.465 | V |
| Vi | Input Voltage | -0.3 | 5.5 | V |
| Vimin | Input Voltage - undershoot2 | -0.6 | - | V |
| Ta, Industrial |
Ambient Operating Temperature |
-40 | 85 | degrees C |
| Tstg | Storage Temperature | -40 | 125 | degrees C |
79RC32332 Features
RC32300 32-bit Microprocessor
Up to 150 MHz operation
Enhanced MIPS-II Instruction Set Architecture (ISA)
Cache prefetch instruction
Conditional move instruction
DSP instructions
Supports big or little endian operation
MMU with 32 page TLB
8KB Instruction Cache, 2-way set associative
2KB Data Cache, 2-way set associative
Cache locking per line
Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
Compatible with a wide variety of operating systems
Local Bus Interface
Up to 75 MHz operation
23-bit address bus
32-bit data bus
Direct control of local memory and peripherals
Programmable system watch-dog timers
Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
Input/Output/Interrupt source
Individually programmable
SDRAM Controller (32-bit memory only)
4 banks, non-interleaved
Up to 512MB total SDRAM memory supported
Implements full, direct control of discrete, SODIMM, or DIMM
memories
Supports 16Mb through 512Mb SDRAM device depths
Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
16550 compatible UART
Baud rate support up to 1.5 Mb/s
Memory & Peripheral Controller
6 banks, up to 8MB per bank
Supports 8-,16-, and 32-bit interfaces
Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
Supports external wait-state generation
8-bit boot PROM support
Flexible I/O timing protocols
Up to 150 MHz operation
Enhanced MIPS-II Instruction Set Architecture (ISA)
Cache prefetch instruction
Conditional move instruction
DSP instructions
Supports big or little endian operation
MMU with 32 page TLB
8KB Instruction Cache, 2-way set associative
2KB Data Cache, 2-way set associative
Cache locking per line
Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
Compatible with a wide variety of operating systems
Local Bus Interface
Up to 75 MHz operation
23-bit address bus
32-bit data bus
Direct control of local memory and peripherals
Programmable system watch-dog timers
Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
Input/Output/Interrupt source
Individually programmable
SDRAM Controller (32-bit memory only)
4 banks, non-interleaved
Up to 512MB total SDRAM memory supported
Implements full, direct control of discrete, SODIMM, or DIMM
memories
Supports 16Mb through 512Mb SDRAM device depths
Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
16550 compatible UART
Baud rate support up to 1.5 Mb/s
Memory & Peripheral Controller
6 banks, up to 8MB per bank
Supports 8-,16-, and 32-bit interfaces
Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
Supports external wait-state generation
8-bit boot PROM support
Flexible I/O timing protocols
79RC32334 Maximum Ratings
| Symbol | Parameter | Min1 | Max1 | Unit |
| VCC | Supply Voltage | -0.3 | 3.465 | V |
| Vi | Input Voltage | -0.3 | 5.5 | V |
| Vimin | Input Voltage - undershoot2 | -0.6 | - | V |
| Ta, Industrial |
Ambient Operating Temperature |
-40 | 85 | degrees C |
| Tstg | Storage Temperature | -40 | 125 | degrees C |
79RC32334 Features
RC32300 32-bit Microprocessor
Up to 150 MHz operation
Enhanced MIPS-II Instruction Set Architecture (ISA)
Cache prefetch instruction
Conditional move instruction
DSP instructions
Supports big or little endian operation
MMU with 32 page TLB
8kB Instruction Cache, 2-way set associative
2kB Data Cache, 2-way set associative
Cache locking per line
Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
Compatible with a wide variety of operating systems
Local Bus Interface
Up to 75 MHz operation
26-bit address bus
32-bit data bus
Direct control of local memory and peripherals
Programmable system watch-dog timers
Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
Input/Output/Interrupt source
Individually programmable
SDRAM Controller (32-bit memory only)
4 banks, non-interleaved
Up to 512MB total SDRAM memory supported
Implements full, direct control of discrete, SODIMM, or DIMM
memories
Supports 16Mb through 512Mb SDRAM device depths
Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
Two 16550 compatible UARTs
Baud rate support up to 1.5 Mb/s
Modem control signals available on one channel
Memory & Peripheral Controller
6 banks, up to 64MB per bank
Supports 8-,16-, and 32-bit interfaces
Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
Supports external wait-state generation
8-bit boot PROM support
Flexible I/O timing protocols
Up to 150 MHz operation
Enhanced MIPS-II Instruction Set Architecture (ISA)
Cache prefetch instruction
Conditional move instruction
DSP instructions
Supports big or little endian operation
MMU with 32 page TLB
8kB Instruction Cache, 2-way set associative
2kB Data Cache, 2-way set associative
Cache locking per line
Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
Compatible with a wide variety of operating systems
Local Bus Interface
Up to 75 MHz operation
26-bit address bus
32-bit data bus
Direct control of local memory and peripherals
Programmable system watch-dog timers
Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
Input/Output/Interrupt source
Individually programmable
SDRAM Controller (32-bit memory only)
4 banks, non-interleaved
Up to 512MB total SDRAM memory supported
Implements full, direct control of discrete, SODIMM, or DIMM
memories
Supports 16Mb through 512Mb SDRAM device depths
Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
Two 16550 compatible UARTs
Baud rate support up to 1.5 Mb/s
Modem control signals available on one channel
Memory & Peripheral Controller
6 banks, up to 64MB per bank
Supports 8-,16-, and 32-bit interfaces
Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
Supports external wait-state generation
8-bit boot PROM support
Flexible I/O timing protocols
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