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79RC32351, 79RC32355, 79RC32364

Table of contents:
Info of 79RC32351
Info of 79RC32355
Info of 79RC32364

79RC32351, 79RC32355, 79RC32364 Selling Leads, Datasheet

MFG:IDT Package Cooled:N/A D/C:09+

79RC32351, 79RC32355, 79RC32364 Datasheet download

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Part Number: 79RC32351

MFG: IDT

Package Cooled: N/A

D/C: 09+

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79RC32351 General Description

The following table lists the functions of the pins provided on the RC32351. Some of the functions listed may be multiplexed onto the same pin. To define the active polarity of a signal, a suffix will be used. Signals ending with an "N" should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
Note: The input pads of the RC32351 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32351's operation.
Also, any input pin left floating can cause a slight increase in power consumption.

79RC32351 Maximum Ratings

Symbol	Parameter	Min1	Max1	Unit
V_CCI/O	I/O Supply Voltage	-0.6	4.0	V
V_CCCore	Core Supply Voltage	-0.3	3.0	V
V_CCP	PLL Supply Voltage	-0.3	3.0	V
Vimin	Input Voltage - undershoot	-0.6	-	V
Vi	I/O Input Voltage	Gnd	V_CCI/O+0.5	V
Ta, Industrial	Ambient Operating Temperature	0	70	degrees C
Tstg	Storage Temperature	-40	125	degrees C

1. Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability
or cause permanent damage to the device.

79RC32351 Features

RC32300 32-bit Microprocessor
Enhanced MIPS-II ISA
Enhanced MIPS-IV cache prefetch instruction
DSP Instructions
MMU with 16-entry TLB
8kB Instruction cache, 2-way set associative
2kB Data cache, 2-way set associative
Per line cache locking
Write-through and write-back cache management
Debug interface through the EJTAG port
Big or little endian support
Interrupt Controller
Allows status of each interrupt to be read and masked
UARTs
Two 16550 Compatible UARTs
Baud rate support up to 1.5 Mb/s
Counter/Timers
Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
32 individually programmable pins:
    each pin programmable as input, output, or alternate function,
    input can be an interrupt or NMI source,
    input can also be active high or active low
4 additional, auxiliary GPIO pins can be configured as input or output
SDRAM Controller
2 memory banks, non-interleaved, 512 MB total
32-bit wide data path
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
SODIMM support
Stays on page between transfers
Automatic refresh generation
Peripheral Device Controller
26-bit address bus
32-bit data bus with variable width support of 8-,16-, or 32-bits
8-bit boot ROM support
6 banks available, up to 64MB per bank
Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices
Supports external wait-state generation, Intel or Motorola style
Write protect capability
Direct control of optional external data transceivers
System Integrity
Programmable system watchdog timer resets system on timeout
Programmable bus transaction times memory and peripheral
    transactions and generates a warm reset on time-out
DMA
14 DMA channels
Services on-chip and external peripherals
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O transfers
Supports flexible descriptor based operation and chaining via
    linked lists of records (scatter / gather capability)
Supports unaligned transfers

79RC32355 Maximum Ratings

Symbol	Parameter	Min1	Max1	Unit
V_CCI/O	I/O supply Voltage	-0.3	3.465	V
V_CCCore	Core Supply Voltage	-0.3	3.0	V
V_CC^P	PLL supply	-0.3	3.0	V
Vimin	Input Voltage - undershoot	-0.6	-	V
VI	I/O Input Voltage	Gnd	V_CCI/O+ 0.6	V
Ta Industrial	Ambient Operating Temperature	-40	85	degrees C
Tstg	Storage Temperature	-40	125	degrees C

79RC32355 Features

RC32300 32-bit Microprocessor
Enhanced MIPS-II ISA
Enhanced MIPS-IV cache prefetch instruction
DSP Instructions
MMU with 16-entry TLB
8KB Instruction Cache, 2-way set associative
2KB Data Cache, 2-way set associative
Per line cache locking
Write-through and write-back cache management
Debug interface through the EJTAG port
Big or Little endian support
Interrupt Controller
Allows status of each interrupt to be read and masked
I²C
Flexible I²C standard serial interface to connect to a variety of peripherals
Standard and fast mode timing support
Configurable 7 or 10-bit addressable slave
UARTs
Two 16550 Compatible UARTs
Baud rate support up to 1.5 Mb/s
Counter/Timers
Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
36 individually programmable pins
Each pin programmable as input, output, or alternate function
Input can be an interrupt or NMI source
Input can also be active high or active low
SDRAM Controller
2 memory banks, non-interleaved, 512 MB total
32-bit wide data path
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
SODIMM support
Stays on page between transfers
Automatic refresh generation
Peripheral Device Controller
26-bit address bus
32-bit data bus with variable width support of 8-,16-, or 32-bits
8-bit boot ROM support
6 banks available, up to 64MB per bank
Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices
Supports external wait-state generation, Intel or Motorola style
Write protect capability
Direct control of optional external data transceivers
System Integrity
Programmable system watchdog timer resets system on time-out
Programmable bus transaction times memory and peripheral transactions and generates a warm reset on time-out
DMA
16 DMA channels
Services on-chip and external peripherals
Supportsmemory-to-memory,memory-to-I/O, and I/O-to-I/O transfers
Supports flexible descriptor based operation and chaining vialinked lists of records (scatter / gather capability)
Supports unaligned transfers
Supports burst transfers
USB
Revision 1.1 compliant
USB slave device controller
Supports a 6th USB endpoint
Full speed operation at 12 Mb/s
Supports control, interrupt, bulk and isochronous endpoints
Supports USB remote wakeup
Integrated USB transceiver
TDM
Serial Time Division Multiplexed (TDM) voice and data inter-face
Provides interface to telephone CODECs and DSPs
Interface to high quality audio A/Ds and D/As with external glue logic
Support 1 to 128 8-bit time slots
Compatible with Lucent CHI, GCI, Mitel ST-bus, K2 and SLD busses
Supports data rates of up to 8.192 Mb/s
Supports internal or external frame generation
Supports multiple non-contiguous active input and output time slots
EJTAG
Run-time Mode provides a standard JTAG interface
Real-Time Mode provides additional pins for real-time trace information
Ethernet
Full duplex support for 10 and 100 Mb/s Ethernet
IEEE 802.3u compatible Media Independent Interface (MII) with serial management interface
IEEE 802.3u auto-negotiation for automatic speed selection
Flexible address filtering modes
64-entry hash table based multicast address filtering
ATM SAR
Can be configured as one UTOPIA level 1 interface or 1UTOPIA level 2 interface with 2 address lines (3 PHYs max)
Supports 25Mb/s and faster ATM
Supports UTOPIA data path interface operation at speeds up to 33 MHz
Supports standard 53-byte ATM cells
Performs HEC generation and checking
Cell processing discards short cells and clips long cells
16 cells worth of buffering
UTOPIA modes: 8 cell input buffer and 8 cell output buffer
Hardware support for CRC-32 generation and checking for AAL5
Hardware support for CRC-10 generation and checking
Virtual caching receive mechanism supports reception of any length packet without CPU intervention on up to eight simulta-neously active receive channels
Frame Mode transmit mechanism supports transmission of any length packet without CPU intervention
System Features
JTAG Interface (IEEE Std. 1149.1 compatible)
208 pin PQFP package
2.5V core supply and 3.3V I/O supply
Up to 180 MHz pipeline frequency and up to 75 MHz bus frequency

79RC32364 General Description

Targeted to a variety of performance-hungry, cost-sensitive embedded applications, the RC32364 is a new low-powered, low-cost member of the Integrated Device Technology, Inc. (IDT) RISController Series of Embedded Microprocessors.

The RC32364 brings 64-bit performance levels to lower cost systems. High performance is achieved through the use of advanced techniques such as large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high-bandwidth, and facilities such as early restart for data cache misses. Also, through IDT proprietary enhancements to the base MIPS architecture, the processor’s performance, in particular applications, is further extended.

The RC32364 is the first member of a new processor family that uses IDT’s proprietary RISCore32300 CPU core. The RISCore32300 core continues IDT’s tradition of high-performance through high-speed pipelines, high-bandwidth caches, and architectural extensions that serve the needs of specific markets; yet the RC32364 provides these capabilities in a low-cost, high-speed 32-bit enhanced MIPS architecture core, enabling a new level of price performance.

Around the RISCore32300, the RC32364 integrates a fully RC5000 compatible memory management unit (MMU), substantial amounts of efficient cache memory, an enhanced debug capability, digital signal processing (DSP) extensions, and a low-cost system interface. The resulting device is well suited to the needs of mid-range communications equipment, xDSL equipment, and consumer devices.

Also, being upwardly software compatible with the RC3000 family, the RC32364 will serve in many of the same applications as well as support applications that require integer DSP functions.

79RC32364 Maximum Ratings

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Symbol	Rating	RC32364 3.3V±5%	RC32364 3.3V±5%	Unit
Symbol	Rating	Commercial	Industrial	Unit
V_TERM	Terminal Voltage with respect to GND	-0.5¹ to 4.0	-0.5¹ to 4.0	V
T_C	Operating Temperature(case)	0 to +85	-40 to +85	°C
T_BIAS	Case Temperature Under Bias	-55 to +125	-55 to +125	°C
T_STG	Storage Temperature	-55 to +125	-55 to +125	°C
I_IN	DC Input Current	20²	20²	mA
I_OUT	DC Output Current	50³	50³	mA

¹. V_IN minimum =-2.0V for pulse width less than 15ns. V_INshould not exceed V_CC +0.5 Volts.
². When V_IN < 0V or V_IN > V_CC
³. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

79RC32364 Features

· High-performance embedded RISControllerTM microprocessor, based on IDT RISCore32300TM 32-bit CPU core
    - Based on MIPS 32 RISC architecture with enhancements
    - Scalar 5-stage pipeline minimizes branch and load delays
    - 66 Million multiply accumulate (MAC) Mul-Add/second @ 133MHz
    - 100 and 133 frequencies
· MIPS 32 (ISA) instruction set architecture
    - MIPS IV compatible conditional move instructions
    - MIPS IV superset PREF (prefetch) instruction
    - Fast multiplier with atomic multiply-add, multiply-sub
    - Count leading zeros/ones instructions
· Large, efficient on-chip caches
    - Separate 8kB Instruction cache and 2kB Data cache
    - 2-way set associative
    - Write-back and write-through support on a per page basis
    - Optional cache locking with “per line” resolution, to facilitate deterministic response
    - Simultaneous instruction and data fetch in each clock cycle, sustained rate, achieves over 1 GB/sec bandwidth
· Flexible RC4000 compatible MMU with 32-page TLB on-chip
    - Variable page size
    - Variable number of locked entries
    - No performance penalty for address translation
· Flexible bus interface allows simple, low-cost designs
    - Bus interface runs at a fraction of pipeline rate
    - Programmable port-width interface (8-,16-, 32-bit memory and I/O regions)
    - Programmable bus turnaround times (BTA)
    - Supports single data or burst transactions
· Improved real-time support
    - Fast interrupt decode
· Low-power operation
    - Active power management: powers down inactive units
    - Typical power 700mW @ 133MHz
    -Stand-by mode <300mW
· Enhanced JTAG interface, for low-cost in-circuit emulation (ICE)
· MIPS architecture ensures applications software compatibility throughout the RISController series of embedded processors
· Industrial temperature range support
· 3.3V operation (core and I/O)

79RC32364 Connection Diagram

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