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CY2DP818, CY2DP818-2, CY2DP818ZC

Table of contents:
Info of CY2DP818
Info of CY2DP818-2
Info of CY2DP818ZC

CY2DP818, CY2DP818-2, CY2DP818ZC Selling Leads, Datasheet

MFG:N/A Package Cooled:N/A D/C:09+

CY2DP818, CY2DP818-2, CY2DP818ZC Picture

CY2DP818, CY2DP818-2, CY2DP818ZC Datasheet download

Five Points

Part Number: CY2DP818

MFG: N/A

Package Cooled: N/A

D/C: 09+

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CY2DP818 Parameters

CY2DP818 Features

Low-voltage operation V_DD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at » 350 MHz–700 Mbps

CY2DP818 General Description

1:8 Clock Fanout Buffer

CY2DP818 Maximum Ratings

Storage Temperature: .............................................................65°C to + 150°C
Ambient Temperature:.................................................................40°C to +85°C
Supply Voltage to Ground Potential (Inputs and V_CC only)............ 0.3V to 4.6V
Supply Voltage to Ground Potential (Outputs only) ............ 0.3V to VDD + 0.3V
DC Input Voltage ................................................................ 0.3V to VDD + 0.3V
DC Output Voltage............................................................... 0.3V to VDD + 0.9V
Power Dissipation...................................................................................... 0.75W

CY2DP818 Features

Low-voltage operation V_DD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at » 350 MHz–700 Mbps

CY2DP818 Typical Application

CY2DP818 Datasheet

CY2DP818 Connection Diagram

CY2DP818-2 Parameters

CY2DP818-2 Features

Low-voltage operation VDD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
Eight pairs of LVPECL outputs with enable/disable
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation up to 350 MHz/700 Mbps

CY2DP818-2 General Description

1:8 Clock Fanout Buffer

CY2DP818-2 Maximum Ratings

Parameter	Description		Condition	Min.	Max.	Unit
V_DD	DC Supply Voltage		Inputs and V_CC	0.3	4.6	V
V_DD	DC Operating Voltage		Outputs	0.3	V_DD +0.3	V
V_IN	DC Input Voltage		Relative to VSS, with or VDD applied	0.3	V_DD +0.3	V
V_OUT	DC Output Voltage		Relative to VSS	0.3	V_DD + 0.9	V
V_TT	Output termination Voltage				V_DD ÷ 2	V
T_S	Temperature, Storage		Non-functional	65	+150	°C
T_A	Temperature,Operating Ambient	Commercial	Functional	0	70	°C
T_A	Temperature,Operating Ambient	Industrial	Functional	40	+85

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

CY2DP818-2 Features

Low-voltage operation VDD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
Eight pairs of LVPECL outputs with enable/disable
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation up to 350 MHz/700 Mbps

CY2DP818-2 Typical Application

CY2DP818-2 Datasheet

CY2DP818-2 Connection Diagram

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