CY2071A

Features:

·Single phase-locked loop architecture
·EPROM programmability
·Factory-programmable (CY2071A, CY2071AI) or fieldprogrammable (CY2071AF, CY2071AFI) device options
·Up to three configurable outputs
·Low-skew, low-jitter, high-accuracy outputs
·Internal loop filter
·Power management (OE)
·Frequency select options
·Configurable 5V or 3.3V operation
·8-pin 150-mil SOIC package


Pinout




Specifications

Supply Voltage ...............................................0.5V to +7.0V
DC Input Voltage ..................................... 0.5V to VDD+0.5V
Storage Temperature ................................. 65°C to +150°C
Max. Soldering Temperature (10 sec) ..........................260°C
Junction Temperature...................................................150°C
Static Discharge Voltage............................................ >2000V


Description

The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, video CD players, games, set-top boxes, and data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and can operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10-MHz to 25-MHz crystals.
Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used.
The CY2071A has one PLL and outputs three factory-EPROM configurable clocks: CLKA, CLKB, and CLKC. The output clocks can originate either from the PLL or the reference, selected dividers thereof. Additionally, pin 8 can be configured to be an Output Enable or a Select input.
The CY2071A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to the manufacturer. Hence, these devices are ideally suited for applications that require multiple, accurate,and stable clocks synthesized from low-cost generators small packages. A hard-disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers.