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FIN101, FIN1017, FIN1018

Table of contents:
Info of FIN101
Info of FIN1017
Info of FIN1018

FIN101, FIN1017, FIN1018 Selling Leads, Datasheet

MFG:Fairchild Package Cooled:TSSOP-3.9-20P D/C:03+

FIN101, FIN1017, FIN1018 Datasheet download

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Part Number: FIN101

MFG: Fairchild

Package Cooled: TSSOP-3.9-20P

D/C: 03+

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FIN1017 General Description

This single driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology.The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data.

The FIN1017 can be paired with its companion receiver,the FIN1018, or with any other LVDS receiver.

FIN1017 Maximum Ratings

Supply Voltage (V_CC)..................................... −0.5V to +4.6V
DC Input Voltage (D_IN) .....................................−0.5V to +6V
DC Output Voltage (D_OUT)............................ −0.5V to +4.7V
Driver Short Circuit Current (I_OSD) .....................Continuous
Storage Temperature Range (T_STG) .......−65°C to +150°C
Max Junction Temperature (T_J) ..................................150°C
Lead Temperature (T_L)
(Soldering, 10 seconds) ............................................260°C
ESD (Human Body Model) ....................................... 6500V
ESD (Bus Pins DOUT+/DOUT− to GND) ................. 10500V
ESD (Machine Model) ............................................... 350V

FIN1017 Features

• Greater than 600Mbs data rate
• 3.3V power supply operation
• 0.5ns maximum differential pulse skew
• 1.5ns maximum propagation delay
• Low power dissipation
• Power-Off protection
• Meets or exceeds the TIA/EIA-644 LVDS standard
• Flow-through pinout simplifies PCB layout
• 8-Lead SOIC and US8 packages save space

FIN1017 Connection Diagram

FIN1018 General Description

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data.

The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

FIN1018 Maximum Ratings

Product	Product status	Eco Status	Pricing*	Package type	Leads	Packing method	Package Marking Convention**
FIN1018K8X	Full Production	RoHS Compliant	$0.53	US8	8	TAPE REEL	Line 1: &2 (2-Digit Date Code) &K Line 2: 1018 Line 3: $Y&Z
FIN1018M	Full Production	Green	$0.50	SOIC	8	RAIL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: FIN Line 3: 1018
FIN1018MX	Full Production	Green	$0.50	SOIC	8	TAPE REEL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: FIN Line 3: 1018

* Fairchild 1,000 piece Budgetary Pricing

** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples

Package marking information for product FIN1018 is available. Click here for more information .

FIN1018 Features

• Greater than 400Mbs data rate
• 3.3V power supply operation
• 0.4ns maximum pulse skew
• 2.5ns maximum propagation delay
• Low power dissipation
• Power-Off protection
• Fail safe protection for open-circuit, shorted and terminated conditions
• Meets or exceeds the TIA/EIA-644 LVDS standard
• Flow-through pinout simplifies PCB layout
• 8-Lead SOIC and US-8 packages save space

FIN1018 Connection Diagram

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