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HIP7010IP, HIP7010P, HIP7020

Table of contents:
Info of HIP7010IP
Info of HIP7010P
Info of HIP7020

HIP7010IP, HIP7010P, HIP7020 Selling Leads, Datasheet

MFG:intersil Package Cooled:HAR D/C:07+

HIP7010IP, HIP7010P, HIP7020 Datasheet download

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Part Number: HIP7010IP

MFG: intersil

Package Cooled: HAR

D/C: 07+

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HIP7020 General Description

The HIP7020 IC is an Integrated I/O Bus Transceiver designed for the SAE Standard J1850 Class B Data Communication Network Interface. The Bus transmits and receives data on a single wire using a 10.4kHz VPWM (Variable Pulse Width Modulated) signal. The HIP7020 serves as an I/O buffer interfacing to 5V CMOS logic. It is designed to operate directly from the 12V battery line of an automobile. The normal Bus voltage swing capability is from 0V to 7.75V at currents greater than 20mA.

As shown in the Block Diagram, the Transmitter TX Input and the Receiver RX Output of the Bus Transceiver Circuit interface to the control logic. The TX input signal is wave shaped for rise time, fall time and amplitude before it is converted from voltage to current. The Wave Shaper with an external programming resistor, RS controls the rise and fall time of the BUS OUT output signal. The current source drive to the Bus is voltage controlled by the Wave Shaped Voltage Reference to a maximum limit as specified for the J1850 Bus and includes short-circuit current limiting.

The HIP7020 Receiver input, BUS IN is connected to the J1850 Bus through an external resistor, RF and has a trip point at one-half of the nominal Bus signal voltage which is 3.875V. The Receiver input is filtered to remove high frequency Bus noise by the external resistor and an internal capacitor. The Receiver Bus signal, after processing, is output at the RX pin by the RX Buffer's open collector driver. The RX output is active low and requires an external pull-up resistor returned to the control logic VCC supply. This prevents power-up of the control logic by the transceiver if VCC supply voltage is removed.

The HIP7020 has a Loop-Back Enable Mode Switch to return diagnostic information for the Bus Transceiver node. For an active low or an open LB EN input, the Transmit/ Receive signals are internally "Looped-Back" to provide a TX to RX return signal path independent of signals on the Bus. A return path validation indicates proper action of the Bus Transceiver apart from the J1850 Bus.

HIP7020 Maximum Ratings

Supply Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . -20V to +24V
Short Term Supply Voltage, VBATT, 1s Max. (Note 2) . . . . . . . +35V
J1850 Bus Input Voltage, VBUS IN . . . . . . . . . . . . . . . . . . . . . ±20V
J1850 Bus Load Current, IBO. . . . . . . . . . . . . . . . . . . .Self-Limiting
TX Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to 7V
RX Logic Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Load Dump (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
BUS Transient Susceptibility . . . . . . . . . . . . . . . . . . . . . . . (Note 3)
ESD: BUS OUT, BATTERY Pins, (Air Gap, Note 4) . . . . . . . . . . . ±9kV
BUS OUT, BATTERY Pins, (Direct, Note 4) . . . . . . . . . . . . . . ±4.5kV
All Other Pins (Direct, Note 4) . . . . . . . . . . . . . . . . . . . . . . . . ±2kV

HIP7020 Features

• J1850 Bus Transceiver for MX Wiring
• 5V CMOS/TTL Logic Interface
• Current Controlled Transmitter Driver
• Controlled Rise/Fall Time of Bus Drive for Both
Voltage and Current
• Bus Drive Capability to Less Than 500W with a 5ms
Load RC Time Constant
• Filtered Bus Input Receiver
• Ground Fault Tolerant for Bus Isolation
• Short Circuit and Over Temperature Protection
• Protection for Reverse Battery, Load Dump
and Latch-Up
• ±9kV ESD Protection BUS OUT and BATTERY Pins
• -40oC to 125oC Operating Range
• Loop-Back Fault Detection Mode
• 4x (41.6kHz) Receive Speed

HIP7020 Typical Application

The circuit of Figure 1 illustrates the essential elements of the J1850 Bus Transceiver in a normal application. For normal J1850 applications, a Bus Transceiver is used at each system node. The Electrical Specifications Table also refers to the peripheral components shown in Figure 1 and the Block Diagram for the HIP7020 Bus Transceiver.

HIP7020 Connection Diagram

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