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MS8128VXMB-45, MS818, MS81V04160

Table of contents:
Info of MS8128VXMB-45
Info of MS818
Info of MS81V04160

MS8128VXMB-45, MS818, MS81V04160 Selling Leads, Datasheet

MFG:MSI Package Cooled:SIP32 D/C:91/92

MS8128VXMB-45, MS818, MS81V04160 Picture

MS8128VXMB-45, MS818, MS81V04160 Datasheet download

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Part Number: MS8128VXMB-45

MFG: MSI

Package Cooled: SIP32

D/C: 91/92

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MS81V04160 General Description

The MS81V04160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out) memories which were designed for 256k x 8-bit high-speed asynchronous read/write operation.

The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory (MSM51V8222A), can be used as a x16 configuration FIFO.

The MS81V04160 is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems.
The MS81V04160 provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The MS81V04160 provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V04160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.

The MS81V04160's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings.

Additionally, the MS81V04160 has a write mask function or input enable function (IE), and read- data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MS81V04160. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture" on a TV screen.

MS81V04160 Maximum Ratings

Parameter	Symbol	Condition	Rating	Unit
Input Output Voltage	V_T	at Ta = 25, VSS	-1.0 to 4.6	V
Output Current	I_OS	Ta = 25	50	mA
Power Dissipation	P_D	Ta = 25	1	W
Operating Temperature	T_opr	-	0 to 70
Storage Temperature	T_stg	-	-55 to 150

MS81V04160 Features

·512 Rows x 512 columns x 8 bits x2
·Fast FIFO(First-In First-Out)Operation :25ns cycle time
·Self refresh(No refresh control is required)
·High speed asynchronous serial access Read/Write Cycle Time 25ns/30ns Access Time 22ns/25ns
·Variable length delay bit (600 to 262215)
·Write mask function (Output enable control)
·Cascading capability by mode setting
·Single power supply:3.3Vp10%
·Package:
100-Pin plastic TQFP(TQFP 100-P-1414-0.50-k)(Product:MS81V04160-xxTB) xx indicates speed rank.

MS81V04160 Connection Diagram

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