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These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
NDS352AP Maximum Ratings
Symbol
Parameter
NDS8410
Units
VDSS VGSS
Drain-Source Voltage Gate-Source Voltage
-30 ±20 ±0.9 ±10 0.5 0.46 -55 to 150
V V A
W
°C
ID
Drain Current Continuous Pulsed
(Note 1a)
PD
Maximum Power Dissipation
(Note 1a) (Note 1b)
TJ,TSTG
Operating and Storage Junction Temperature Range
NDS352AP Features
·-0.9 A, -30 V. RDS(ON) = 0.5 W @ VGS = -4.5 VRDS(ON) = 0.3 W @ VGS = -10 V. ·Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. ·High density cell design for extremely low RDS(ON). ·Exceptional on-resistance and maximum DC current capability.