SDA9205-2, SDA9206, SDA9206A31 Selling Leads, Datasheet
MFG:Infineon Package Cooled:0 D/C:2350
SDA9205-2, SDA9206, SDA9206A31 Datasheet download
Part Number: SDA9205-2
MFG: Infineon
Package Cooled: 0
D/C: 2350
SDA9205-2, SDA9206, SDA9206A31
- Table of contents:
Info of SDA9205-2
Info of SDA9206
Info of SDA9206A31
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About SDA9205-2
PDF/DataSheet Download
Datasheet: SDA9205-2
File Size: 581136 KB
Manufacturer: SIEMENS [Siemens Semiconductor Group]
Download : Click here to Download
About SDA9206
PDF/DataSheet Download
Datasheet: SDA9206
File Size: 543073 KB
Manufacturer: Infineon
Download : Click here to Download
About SDA01
PDF/DataSheet Download
Datasheet: SDA01
File Size: 21011 KB
Manufacturer: SANKEN [Sanken electric]
Download : Click here to Download
SDA9205-2 General Description
The SDA 9205-2 is a single monolithic IC containing three separate 8-bit analog to digital converters for video (YUV) applications. It utilizes an advanced VLSI 1.2 m CMOS process providing 30-MHz sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several control inputs, compatible to inputs of all Siemens Featureboxes, Siemens TV-SAM, and CCIR 656 output format.
The ADCs have no missing codes over the full operating temperature range of 0 to + 70 °C. Operation is from + 5 V DC-power supply.
SDA9205-2 Maximum Ratings
| Parameter | Symbol | Limit Values | Unit | |
| min. | max. | |||
| Supply voltages1) | VCC, VDD | 6.5 | V | |
| Input voltage range all inputs | VI | 0.3 | VCC + 0.3 | V |
| Ambient temperature | TA | 0 | 70 | °C |
| Storage temperature | Tstg | 55 | 125 | °C |
SDA9205-2 Features
Three equivalent CMOS A/D converters on chip
30-MHz sample rate
8-bit resolution
No external sample & hold required
On-chip input buffer for each analog channel
Internal clamping circuits for each of the ADCs
Different digital output multiplex formats:
3 independent unmultiplexed 8-bit outputs
Multiplexed formats compatible to inputs of all Siemens Featureboxes and Siemens TV-SAM
CCIR 656 output format
Overflow and underflow outputs
30-MHz sample rate
8-bit resolution
No external sample & hold required
On-chip input buffer for each analog channel
Internal clamping circuits for each of the ADCs
Different digital output multiplex formats:
3 independent unmultiplexed 8-bit outputs
Multiplexed formats compatible to inputs of all Siemens Featureboxes and Siemens TV-SAM
CCIR 656 output format
Overflow and underflow outputs
SDA9205-2 Connection Diagram
SDA9206 General Description
The SDA 9206 is a single monolithic IC containing three separate 8-Bit A/D converters for video (YUV) applications and a clock sync generator which is delivering the sample clock for the A/D converters. It utilizes an advanced VLSI 0.5 mm CMOS process providing 30 MHz sampling rates at 8-Bits.
SDA9206 Maximum Ratings
| Parameter | Symbol | Limit Values | Unit | Remarks | |
| min. | max. | ||||
| Storage temperature | Tstg | - 40 | 125 | ||
| Soldering temperature | Tsold | 260 | |||
| Soldering time | 10 | sec | |||
| Input/output voltage | VI/Q | VSSQ - 0.3V | VDDQ + 0.3V | 1 | Not valid for I2C-Bus pins |
| Input/output voltage I2C-pins 33, 34 (SCL, SDA) |
VI/Q, I2C | VSSQ - 0.3V | 6 V | 1 | |
| Power supply voltage | VDD, VADDx, VDDQ, VDDDTO |
- 0.3 | 6 | V | |
| Total power dissipation | Ptot | 1.25 | W | ||
| Latch-up protection | - 100 | 100 | mA | All inputs/outputs | |
| ESD protection | ESD | - 1 | 1 | kV | MIL STD 883C method 3015-6, 100 pF, 1500 W |
SDA9206 Features
• Three equivalent CMOS A/D converters on chip
• 30 MHz sampling rate
• 8-Bit resolution
• No external sample & hold required
• Internal clamping circuits for each of the ADCs
• Internal amplification of input signals can be set by I2C Bus
• Internal pre-filtering of analog input signals
• High performance decimation filters
• Two data sampling modes (4:2:2 and 4:1:1)
• 3 output data interfaces
- CCIR 656 interface (8 wires)
- Parallel data interface (2 x 8 wires)
- Quasi Parallel data interface (8 + 4 wires)
• Overflow and underflow I2C status bits
• On-chip sync and clock generation
• Separate SYNC input with clamping for sync and clock generation (max. line frequency of SYNC input: 38 kHz)
• positive and negative polarity of SYNC signal (switchable by I2C Bus)
• Lock-in behavior can be set via I2C Bus
• Frequency generator function possible with digitally adjustable frequency
• Clock generation for single and double line input frequencies supported (1fh / 2fh mode)
• Vertical noise suppression and 50/60 Hz detection (for 1fh mode only)
SDA9206 Connection Diagram
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