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T430N50E, T4312816B, T431616D

Table of contents:
Info of T430N50E
Info of T4312816B
Info of T431616D

T430N50E, T4312816B, T431616D Selling Leads, Datasheet

MFG:TEMTECH D/C:07+

T430N50E, T4312816B, T431616D Datasheet download

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Part Number: T430N50E

MFG: TEMTECH

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D/C: 07+

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T4312816B General Description

The T4312816B SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The T4312816B provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

T4312816B Features

• Fast access time from clock: 5/5.4 ns
• Fast clock rate: 166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 2M word x 16-bit x 4-bank
• Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• Single +3.3V power supply
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
• Lead-free package is available

T4312816B Connection Diagram

T431616D General Description

The T431616D/E SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The T431616D/E provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

T431616D Features

• Fast access time: 5/6/7 ns
• Fast clock rate: 200/166/143 MHz
• Self refresh mode: standard and low power
• Internal pipelined architecture
• 512K word x 16-bit x 2-bank
• Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
• Individual byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• JEDEC standard +3.3V±0.3V power supply
• Interface: LVTTL
• 50-pin 400 mil plastic TSOP II package
• 60-ball, 6.4x10.1mm VFBGA package
• Lead Free Package available for both TSOP II and VFBGA
• Low Operating Current for T431616E

T431616D Connection Diagram

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