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U6216B, U6220B, U6223B

Table of contents:
Info of U6216B
Info of U6220B
Info of U6223B

U6216B, U6220B, U6223B Selling Leads, Datasheet

MFG:TFK Package Cooled:SOP16S D/C:386

U6216B, U6220B, U6223B Datasheet download

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Part Number: U6216B

MFG: TFK

Package Cooled: SOP16S

D/C: 386

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U6216B General Description

The U6216B has the following features including Non oscillating;1.3 GHz divide-by-8 prescalerintegrated(can be ommitted);15-bit counter accepts input frequencies up to 170 MHz;5 switching outputs (open collector);4 addresses selectable at pin 8 for multituner application;62.5 kHz(-1.3 GHz)/ 7. 8125 kHz(-170 MHz) tuningsteps;Electrostatic protection according to MIL-STD 883.

The U6216B is a single chip frequency synthesizer with unidirectional I2C bus control.This IC contains a high frequency prescaler which can be switched off.Meet all present and future national and international statutory requirements.Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol(1987 ) and its London Amendments(1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite).

U6216B Maximum Ratings

U6216B Features

U6220B General Description

The U6220B is a single chip frequency synthesizer with I2C bus and 3-wire bus control (universal bus). This IC contains a high frequency prescaler, a crystal oscillator, a switchable reference divider, 5 open collector switching outputs and an additional mixer switch output for band switching. The U6220B is especially designed for low cost, high performance 2-band and EasyLink tuners (please see application note ANT017 'Semiconductors for TV Tuners - The New EasyLink Concept').

U6220B Maximum Ratings

Parameters	Test Conditions / Pins	Symbol	Min.	Max.	Unit
Supply voltage	Pin 12	VS	0.3	6	V
RF input voltage	Pins 13 and 14	RFi	0.3	V_S + 0.3	V
Crystal oscillator voltage	Pin 2	Q1	0.3	V_S + 0.3	V
Charge pump output voltage	Pin 1	PD	0.3	V_S + 0.3	V
Active filter output voltage	Pin 16	VD	0.3	V_S + 0.3	V
Bus input/ output voltage	Pins 4 and 5	VSDA,SCL	1	6	V
SDA output current	Open collector Pin 4	ISDA	0.3	5	mA
Address select / ENA voltage	Pin 3	VAS/ENA	0.3	V_S + 0.3	V
Mixer switch voltage	Pin 11	MS	1	V_S + 0.3	V
Port output current	Open collector, Pins 6, 8-10		1	15	mA
Port output current	Open collector, Pin 7	VHF L/H		40	mA
Total port output current	Open collector, Pins 6 to 10			50	mA
Port output voltage	In off state, Pins 6 to 10		0.3 0.3	14 6	V V
Junction temperature	In on state	T_jmax	40	150	°C
Storage temperature		T_stg	40	150	°C

U6220B Features

1.3 GHz divide-by-8 prescaler integrated
EasyLink interface to MOSMIC and mixer IC
Universal bus:
    I2C bus or 3-wire bus
    I2C bus software compatible to U6204B
    3-wire bus software compatible to U6359B (18 bit)
I2C bus mode:
    5 port outputs (open collector)
    4 addresses selectable at Pin 3 for multituner application
3-wire bus mode:
    4 port outputs (open collector)
    Lock-signal output (open collector)
Low power consumption (typ. 5 V / 20 mA)
Electrostatic protection according to MIL-STD 883
SO16 small package

U6220B Connection Diagram

U6223B General Description

The U6223B has the following features including Only one device for 3-wire bus applications and I2C bus applications necessary (universal bus);High input frcqucncy of 2.9 GHz applicablc for all TV satellites;Low powcr consumption (typical 5 V/23 mA);Electrostatic protection according to MIL-STD 883.

The U6223B is programmed via a 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pins 4, 5 and 10 are used as SDA, SCL and address select inputs in I2C bus mode and as data, clock and enable inputs in 3-wire bus mode. The data includes the scaling factor SF (15-bit) and switching output information. In I2C-bus mode, there are some additional functions for testing of the device included.The U6223B is function and pin equiralent to the U6225B apart from the switchable reference divider. A typical application is shown on page 12. All input/ output interface circuits are shown on page 9. Some special features which are related to test- and alignment procedures for tuner production, ai-e explained together within the following bus mode description.The charge pump current can only be controlled in I2C bus mode. In 3-wire bus mode, there is always the high charge pump current active. The OS-bit function disables the complete PLL function. This enables the tuner alignment by supplying the tuning voltage directly through the 30 V supply voltage of the tuner.

When the U6225B-B is controlled via 3-wire bus format,then DATA, CLOCK and ENABLE signals are fed into the SDA, SCL and AS/ENA fines respectively. The diagram `3-WIRE-BUS PULSE DIAGRAM,shows the dales formal. The dales consist of a single word, which contains the programmable divider and switch information. The data is only clocked into the internal data shift register on the negative clock transition during the enable lung period on the negative clock transition.During enable low pcriods, the clock input is disabled.New data words are only acccptcd by the intcrnal data latches from the shift register on a ncgativc transition of the enable signal if exactly ninctccn clock pulscs were sent during the high period. The data sequence and the timing is described in the following diagrams.

U6223B Maximum Ratings

U6223B Features

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