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ZL50019QC, ZL50019QCG1, ZL50020

Table of contents:
Info of ZL50019QC
Info of ZL50019QCG1
Info of ZL50020

ZL50019QC, ZL50019QCG1, ZL50020 Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:0631+ D/C:QFP

ZL50019QC, ZL50019QCG1, ZL50020 Datasheet download

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Part Number: ZL50019QC

MFG: ZARLINK

Package Cooled: 0631+

D/C: QFP

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ZL50020 General Description

The ZL50020 is a maximum 2048 x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64kbps and Nx64kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. The ZL50020 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored.

The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 2¹⁵-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.

The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors.

The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

ZL50020 Maximum Ratings

Parameter	Symbol	Min.	Max.	Units
I/O Supply Voltage Core Supply Voltage Input Voltage Input Voltage (5V-tolerant inputs) Continuous Current at Digital Outputs Package Power Dissipation Storage Temperature	V_{DD_IO} V_{DD_CORE} V_{I_3V} V_{I_5V} I_o P_D T_S	-0.5 -0.5 -0.5 -0.5 - 55	5.0 2.5 V_DD +0.5 7.0 15 1.5 +125	V V V V mA W

*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

ZL50020 Features

·2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192Mbps and 16.384Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384Mbps
·32 serial TDM input, 32 serial TDM output streams
·Output streams can be configured as bidirectional for connection to backplanes
·Exceptional input clock cycle to cycle variation tolerance (20ns for all rates)
·Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384Mbps. Input and output data rates can differ
·Per-stream high impedance control outputs (STOHZ) for 16 output streams
·Per-stream input bit delay with flexible sampling point selection
·Per-stream output bit and fractional bit advancement
·Per-channel ITU-T G.711 PCM A-Law/-Law Translation
·Four frame pulse and four reference clock outputs
·Three programmable delayed frame pulse outputs
·Input clock: 4.096MHz, 8.192MHz, 16.384MHz
·Input frame pulses:61ns, 122ns, 244ns
·Per-channel constant or variable throughput delay for frame integrity and low latency applications
·Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151

ZL50020 Typical Application

·PBX and IP-PBX
·Small and medium digital switching platforms
·Remote access servers and concentrators
·Wireless base stations and controllers
·Multi service access platforms
·Digital Loop Carriers
·Computer Telephony Integration

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