Synopsys Announced DesignWare Embedded Memory and Logic Library IP for TSMC’s 28nm SoCs

Published:2012/2/20 1:20:00 Author:Phyllis From:SeekIC

Synopsys has announced immediate availability of DesignWare Embedded Memory and Logic Library IP for TSMC’s 28nm high performance and high performance for mobile process technologies. Designed to deliver high performance with low leakage and active power, the libraries give engineers the ability to optimize their entire system-on-chip (SoC) design for speed and energy efficiency.

Combined with the embedded test and repair technology of the DesignWare STAR Memory System, Synopsys’ embedded memories and standard cell libraries offer designers an advanced, comprehensive IP solution for creating high performance, low-power 28nm SoCs with reduced test and manufacturing costs. DesignWare 28nm Logic Libraries take advantage of multiple threshold variants and gate length bias combinations to deliver optimal performance and power results for a wide variety of SoC applications. These libraries offer multiple, synthesis-friendly cell sets and router-friendly standard cell library architectures designed for multi-GHz performance with minimal die area and high manufacturing yield.

Power Optimization Kits (POKs) provide designers with advanced power management capabilities supported by popular low-power design flows, including shut-down, multi-voltage and dynamic voltage frequency scaling (DVFS). For power-sensitive applications such as mobile devices, all of Synopsys’ 28nm memories incorporate source biasing and multiple power management modes that significantly reduce leakage and dynamic power dissipation. Synopsys’ ultra high-density two-port SRAM and 16 Mbit single-port SRAM compilers further reduce area and leakage by up to 40% compared to standard high-density memories, enabling SoC developers to implement memories with a differentiated blend of high performance, small area and extremely low power.

Synopsys, Inc. provides core electronic design automation (EDA) solutions primarily in the United States, Europe, Japan, and the rest of Asia Pacific. Its EDA solutions include Galaxy Design platform for use in the design of an integrated circuit (IC); Discovery Verification platform for use in the verification of an IC behavior; and FPGA design complex chips products that are customized or programmed to perform a specific function after they are manufactured. The company offers system-level solutions, including Platform Architect that enables exploration of SoC architectural trade-offs; SPW and System Studio solutions for algorithm design; Processor Designer solutions for custom processor design; Synphony Model and C Compiler solutions for high-level synthesis; Virtualizer tool and transaction-level models, which enable the creation of virtual prototypes; and HAPS FPGA-based prototyping systems that integrate hardware and software tools with real-world interfaces to enable hardware-software integration and full system validation. Additionally, it provides consulting and design services for various phases of the SoC development process.

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