Netronome Devotes to Saving Power Consumption for Customers

Published:2012/5/16 2:15:00 Author:Li xiao na From:SeekIC

With Cadence’s latest Encounter 11.1 technology，Netronome designers gained 29% reduction in power consumption；therefore, it can provide performance advantage on its low-power "green" SoCs targeting the secure virtual cloud and data center markets.

The OEM customers of Netronome all have tremendous constraints on power budget, so Netronome have to optimize its high-performance 40Gbps NFPs for low-power consumption for use in their customers’ switch, routers, load balancing, and cyber-security platforms.

The complete Cadence Encounter RTL-to-GDSII flow allows Netronome to tape out a complex 1.4-GHz 40-core micro-engine-based network flow processor on schedule and gain a 29% power savings and 10% improvement in timing.

Netronome’s newly integrated Clock Concurrent Optimization (CCOpt) technology in the Encounter flow and its unique ability to optimize clocks and data-path eliminate the need of several manual designs and achieve superior performance, power, and area results on their design. What is more, the tasks of Netronome engineers include improving chip efficiencies across multi-mode, multi-corner, and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements.

Clocks are the most important part of all digital chips, and a fundamentally different approach to clock construction and optimization was needed. The gap between pre-and post-CTS design timing is becoming large, so traditional clock tree synthesis tools and methodologies are not enough for advanced mode, high-performance designs. By re-focusing CTS directly on timing, the CCOpt technology can bridge the gap.

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