Design Your Own IC: Prototyping with CPLDs （part 2）

Published:2011/7/22 2:29:00 Author:Amy From:SeekIC

by Paul Goossens

Experimenter’s board

Our experimenter’s board has a rea­sonably simple design. Nevertheless, it has more than enough I/O for per­forming our initial experiments with CPLDs. Naturally, all of the relevant pins of the CPLD are brought out via several connectors, to allow external hardware to work together with the board afterwards.

The schematic diagram, which is shown in Figure 3, is fairly simple. The supply voltage of approximately 9 Vqq is applied to connector Kl. IC2 and its surrounding components provide the 5-V operating voltage for the entire cir­cuit. LED Dll and R25 provide a ’power on’ indication. The CPLD is shown in the schematic diagram as IC1. The JTAG program­ming interface is brought out via K2. The pin layout of this connector is com­patible with the Altera ByteBlaster, which means it is also compatible with the Elektoi Electronics Parallel-to-JTAG interface (see the September 2002 issue, page 34). The reset circuit is formed by RC network R1/C12. Finally, an oscillator is implemented using R21, R22, C13, C14 and XI. The manner in which these components can be used together with the CPLD to make an oscillator is described later on in the examples.




A certain amount of simple I/O is indispensable on every experi­menter’s board. IC3 is a buffer that boosts several signals from the CPLD and uses them to drive LEDs D1-D8. IC4 performs a similar function for driving a 7-segment display. If these I/O functions are not desired, they can be decoupled from the CPLD by removing jumper JP1. We decided to use eight switches for the inputs. To make your initial experi­menting relatively easy, these eight switches (S1-S8) are equipped with a debouncer circuit. This function is pro­vided by IC5-IC8. These inputs are connected to the CPLD via IC9, but here again this part of the circuit can be decoupled from the CPLD. In this case, JP2 is responsible for coupling the signals to the CPLD. Finally, connectors K3 through K6 make all relevant CPLD signals available to the outside world.

Construction

The double-sided printed circuit board shown in Figure 4 is generously dimen­sioned in order to keep everything readily accessible. All connectors are placed at the edge of the circuit board. Fitting the components to the circuit board should not present any difficul­ties. Anyone who is interested in CPLDs will certainly have already built other circuit boards. When fitting the components, you primarily have to pay attention to the proper orientation of the ICs, LEDs and electrolytic capacitors. Sockets are definitely recom­mended for the ICs, and a suitable 84-pin PLCC socket is essential for the CPLD. Make sure that the bevelled cor­ner of the PLCC socket is correctly positioned on the circuit board (refer to the component overlay), since it can also be fitted incorrectly into the holes in the circuit board. Incidentally, the CPLD fits into the socket in only one orientation.




Portions of the circuit that are not used can be disconnected from the CPLD by means of jumpers JP1 and JP2. Natu­rally, you can also simply omit the unneeded components. For instance, IC4 along with LD1 and R11-R18 can be omitted if the 7-segment display is not necessary. The same holds true for IC3 together with D1-D8 and R2-R9 if you don’t need any LED indicators. As for the switches, you only need to fit the ones that are needed for the initial experiments.

The voltage regulator (IC2) is fitted flat against the board and secured using a small screw and nut. An additional heat sink is not necessary, at least as long as any additional hardware con­nected to the board does not draw too much current.

The supply voltage can be provided by a mains adapter that supplies approx­imately 9-15 V at a current of at least 100 mA. This value applies to the experimenter’s board by itself and must be increased by the amount of current drawn by any additional hard­ware that may be present.

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